1 # Copyright (c) 2012-2014 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2013 Amin Farmahini-Farahani
14 # Copyright (c) 2015 University of Kaiserslautern
15 # All rights reserved.
17 # Redistribution and use in source and binary forms, with or without
18 # modification, are permitted provided that the following conditions are
19 # met: redistributions of source code must retain the above copyright
20 # notice, this list of conditions and the following disclaimer;
21 # redistributions in binary form must reproduce the above copyright
22 # notice, this list of conditions and the following disclaimer in the
23 # documentation and/or other materials provided with the distribution;
24 # neither the name of the copyright holders nor the names of its
25 # contributors may be used to endorse or promote products derived from
26 # this software without specific prior written permission.
28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 # Authors: Andreas Hansson
45 from m5
.params
import *
46 from AbstractMemory
import *
48 # Enum for memory scheduling algorithms, currently First-Come
49 # First-Served and a First-Row Hit then First-Come First-Served
50 class MemSched(Enum
): vals
= ['fcfs', 'frfcfs']
52 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
53 # channel, rank, bank, row and column, respectively, and going from
54 # MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
55 # suitable for an open-page policy, optimising for sequential accesses
56 # hitting in the open row. For a closed-page policy, RoCoRaBaCh
57 # maximises parallelism.
58 class AddrMap(Enum
): vals
= ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
60 # Enum for the page policy, either open, open_adaptive, close, or
62 class PageManage(Enum
): vals
= ['open', 'open_adaptive', 'close',
65 # DRAMCtrl is a single-channel single-ported DRAM controller model
66 # that aims to model the most important system-level performance
67 # effects of a DRAM without getting into too much detail of the DRAM
69 class DRAMCtrl(AbstractMemory
):
71 cxx_header
= "mem/dram_ctrl.hh"
73 # single-ported on the system interface side, instantiate with a
74 # bus in front of the controller for multiple ports
75 port
= SlavePort("Slave port")
77 # the basic configuration of the controller architecture, note
78 # that each entry corresponds to a burst for the specific DRAM
79 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
80 # the cacheline size or request/packet size
81 write_buffer_size
= Param
.Unsigned(64, "Number of write queue entries")
82 read_buffer_size
= Param
.Unsigned(32, "Number of read queue entries")
84 # threshold in percent for when to forcefully trigger writes and
85 # start emptying the write buffer
86 write_high_thresh_perc
= Param
.Percent(85, "Threshold to force writes")
88 # threshold in percentage for when to start writes if the read
90 write_low_thresh_perc
= Param
.Percent(50, "Threshold to start writes")
92 # minimum write bursts to schedule before switching back to reads
93 min_writes_per_switch
= Param
.Unsigned(16, "Minimum write bursts before "
96 # scheduler, address map and page policy
97 mem_sched_policy
= Param
.MemSched('frfcfs', "Memory scheduling policy")
98 addr_mapping
= Param
.AddrMap('RoRaBaCoCh', "Address mapping policy")
99 page_policy
= Param
.PageManage('open_adaptive', "Page management policy")
101 # enforce a limit on the number of accesses per row
102 max_accesses_per_row
= Param
.Unsigned(16, "Max accesses per row before "
105 # size of DRAM Chip in Bytes
106 device_size
= Param
.MemorySize("Size of DRAM chip")
108 # pipeline latency of the controller and PHY, split into a
109 # frontend part and a backend part, with reads and writes serviced
110 # by the queues only seeing the frontend contribution, and reads
111 # serviced by the memory seeing the sum of the two
112 static_frontend_latency
= Param
.Latency("10ns", "Static frontend latency")
113 static_backend_latency
= Param
.Latency("10ns", "Static backend latency")
115 # the physical organisation of the DRAM
116 device_bus_width
= Param
.Unsigned("data bus width in bits for each DRAM "\
118 burst_length
= Param
.Unsigned("Burst lenght (BL) in beats")
119 device_rowbuffer_size
= Param
.MemorySize("Page (row buffer) size per "\
121 devices_per_rank
= Param
.Unsigned("Number of devices/chips per rank")
122 ranks_per_channel
= Param
.Unsigned("Number of ranks per channel")
124 # default to 0 bank groups per rank, indicating bank group architecture
126 # update per memory class when bank group architecture is supported
127 bank_groups_per_rank
= Param
.Unsigned(0, "Number of bank groups per rank")
128 banks_per_rank
= Param
.Unsigned("Number of banks per rank")
129 # only used for the address mapping as the controller by
130 # construction is a single channel and multiple controllers have
131 # to be instantiated for a multi-channel configuration
132 channels
= Param
.Unsigned(1, "Number of channels")
134 # For power modelling we need to know if the DRAM has a DLL or not
135 dll
= Param
.Bool(True, "DRAM has DLL or not")
137 # DRAMPower provides in addition to the core power, the possibility to
138 # include RD/WR termination and IO power. This calculation assumes some
139 # default values. The integration of DRAMPower with gem5 does not include
140 # IO and RD/WR termination power by default. This might be added as an
141 # additional feature in the future.
143 # timing behaviour and constraints - all in nanoseconds
145 # the base clock period of the DRAM
146 tCK
= Param
.Latency("Clock period")
148 # the amount of time in nanoseconds from issuing an activate command
149 # to the data being available in the row buffer for a read/write
150 tRCD
= Param
.Latency("RAS to CAS delay")
152 # the time from issuing a read/write command to seeing the actual data
153 tCL
= Param
.Latency("CAS latency")
155 # minimum time between a precharge and subsequent activate
156 tRP
= Param
.Latency("Row precharge time")
158 # minimum time between an activate and a precharge to the same row
159 tRAS
= Param
.Latency("ACT to PRE delay")
161 # minimum time between a write data transfer and a precharge
162 tWR
= Param
.Latency("Write recovery time")
164 # minimum time between a read and precharge command
165 tRTP
= Param
.Latency("Read to precharge")
167 # time to complete a burst transfer, typically the burst length
168 # divided by two due to the DDR bus, but by making it a parameter
169 # it is easier to also evaluate SDR memories like WideIO.
170 # This parameter has to account for burst length.
171 # Read/Write requests with data size larger than one full burst are broken
172 # down into multiple requests in the controller
173 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
174 # With bank group architectures, tBURST represents the CAS-to-CAS
175 # delay for bursts to different bank groups (tCCD_S)
176 tBURST
= Param
.Latency("Burst duration (for DDR burst length / 2 cycles)")
178 # CAS-to-CAS delay for bursts to the same bank group
179 # only utilized with bank group architectures; set to 0 for default case
180 # tBURST is equivalent to tCCD_S; no explicit parameter required
181 # for CAS-to-CAS delay for bursts to different bank groups
182 tCCD_L
= Param
.Latency("0ns", "Same bank group CAS to CAS delay")
184 # time taken to complete one refresh cycle (N rows in all banks)
185 tRFC
= Param
.Latency("Refresh cycle time")
187 # refresh command interval, how often a "ref" command needs
188 # to be sent. It is 7.8 us for a 64ms refresh requirement
189 tREFI
= Param
.Latency("Refresh command interval")
191 # write-to-read, same rank turnaround penalty
192 tWTR
= Param
.Latency("Write to read, same rank switching time")
194 # read-to-write, same rank turnaround penalty
195 tRTW
= Param
.Latency("Read to write, same rank switching time")
197 # rank-to-rank bus delay penalty
198 # this does not correlate to a memory timing parameter and encompasses:
199 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
200 # different rank bus delay
201 tCS
= Param
.Latency("Rank to rank switching time")
203 # minimum row activate to row activate delay time
204 tRRD
= Param
.Latency("ACT to ACT delay")
206 # only utilized with bank group architectures; set to 0 for default case
207 tRRD_L
= Param
.Latency("0ns", "Same bank group ACT to ACT delay")
209 # time window in which a maximum number of activates are allowed
210 # to take place, set to 0 to disable
211 tXAW
= Param
.Latency("X activation window")
212 activation_limit
= Param
.Unsigned("Max number of activates in window")
214 # time to exit power-down mode
215 # Exit power-down to next valid command delay
216 tXP
= Param
.Latency("0ns", "Power-up Delay")
218 # Exit Powerdown to commands requiring a locked DLL
219 tXPDLL
= Param
.Latency("0ns", "Power-up Delay with locked DLL")
221 # time to exit self-refresh mode
222 tXS
= Param
.Latency("0ns", "Self-refresh exit latency")
224 # time to exit self-refresh mode with locked DLL
225 tXSDLL
= Param
.Latency("0ns", "Self-refresh exit latency DLL")
227 # Currently rolled into other params
228 ######################################################################
230 # tRC - assumed to be tRAS + tRP
232 # Power Behaviour and Constraints
233 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
234 # defined as VDD and VDD2. Each current is defined for each voltage domain
235 # separately. For example, current IDD0 is active-precharge current for
236 # voltage domain VDD and current IDD02 is active-precharge current for
237 # voltage domain VDD2.
238 # By default all currents are set to 0mA. Users who are only interested in
239 # the performance of DRAMs can leave them at 0.
241 # Operating 1 Bank Active-Precharge current
242 IDD0
= Param
.Current("0mA", "Active precharge current")
244 # Operating 1 Bank Active-Precharge current multiple voltage Range
245 IDD02
= Param
.Current("0mA", "Active precharge current VDD2")
247 # Precharge Power-down Current: Slow exit
248 IDD2P0
= Param
.Current("0mA", "Precharge Powerdown slow")
250 # Precharge Power-down Current: Slow exit multiple voltage Range
251 IDD2P02
= Param
.Current("0mA", "Precharge Powerdown slow VDD2")
253 # Precharge Power-down Current: Fast exit
254 IDD2P1
= Param
.Current("0mA", "Precharge Powerdown fast")
256 # Precharge Power-down Current: Fast exit multiple voltage Range
257 IDD2P12
= Param
.Current("0mA", "Precharge Powerdown fast VDD2")
259 # Precharge Standby current
260 IDD2N
= Param
.Current("0mA", "Precharge Standby current")
262 # Precharge Standby current multiple voltage range
263 IDD2N2
= Param
.Current("0mA", "Precharge Standby current VDD2")
265 # Active Power-down current: slow exit
266 IDD3P0
= Param
.Current("0mA", "Active Powerdown slow")
268 # Active Power-down current: slow exit multiple voltage range
269 IDD3P02
= Param
.Current("0mA", "Active Powerdown slow VDD2")
271 # Active Power-down current : fast exit
272 IDD3P1
= Param
.Current("0mA", "Active Powerdown fast")
274 # Active Power-down current : fast exit multiple voltage range
275 IDD3P12
= Param
.Current("0mA", "Active Powerdown fast VDD2")
277 # Active Standby current
278 IDD3N
= Param
.Current("0mA", "Active Standby current")
280 # Active Standby current multiple voltage range
281 IDD3N2
= Param
.Current("0mA", "Active Standby current VDD2")
283 # Burst Read Operating Current
284 IDD4R
= Param
.Current("0mA", "READ current")
286 # Burst Read Operating Current multiple voltage range
287 IDD4R2
= Param
.Current("0mA", "READ current VDD2")
289 # Burst Write Operating Current
290 IDD4W
= Param
.Current("0mA", "WRITE current")
292 # Burst Write Operating Current multiple voltage range
293 IDD4W2
= Param
.Current("0mA", "WRITE current VDD2")
296 IDD5
= Param
.Current("0mA", "Refresh current")
298 # Refresh Current multiple voltage range
299 IDD52
= Param
.Current("0mA", "Refresh current VDD2")
301 # Self-Refresh Current
302 IDD6
= Param
.Current("0mA", "Self-refresh Current")
304 # Self-Refresh Current multiple voltage range
305 IDD62
= Param
.Current("0mA", "Self-refresh Current VDD2")
307 # Main voltage range of the DRAM
308 VDD
= Param
.Voltage("0V", "Main Voltage Range")
310 # Second voltage range defined by some DRAMs
311 VDD2
= Param
.Voltage("0V", "2nd Voltage Range")
313 # A single DDR3-1600 x64 channel (one command and address bus), with
314 # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
315 # an 8x8 configuration.
316 class DDR3_1600_x64(DRAMCtrl
):
317 # size of device in bytes
318 device_size
= '512MB'
320 # 8x8 configuration, 8 devices each with an 8-bit interface
323 # DDR3 is a BL8 device
326 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
327 device_rowbuffer_size
= '1kB'
329 # 8x8 configuration, so 8 devices
333 ranks_per_channel
= 2
335 # DDR3 has 8 banks in all configurations
341 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
356 # Greater of 4 CK or 7.5 ns
359 # Greater of 4 CK or 7.5 ns
362 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
365 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
368 # <=85C, half for >85C
371 # Current values from datasheet
380 # A single HMC-2500 x32 model based on:
381 # [1] DRAMSpec: a high-level DRAM bank modelling tool
382 # developed at the University of Kaiserslautern. This high level tool
383 # uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
384 # estimate the DRAM bank latency and power numbers.
385 # [2] A Logic-base Interconnect for Supporting Near Memory Computation in the
386 # Hybrid Memory Cube (E. Azarkhish et. al)
387 # Assumed for the HMC model is a 30 nm technology node.
388 # The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
390 # Each layer has 16 vaults and each vault consists of 2 banks per layer.
391 # In order to be able to use the same controller used for 2D DRAM generations
392 # for HMC, the following analogy is done:
393 # Channel (DDR) => Vault (HMC)
394 # device_size (DDR) => size of a single layer in a vault
395 # ranks per channel (DDR) => number of layers
396 # banks per rank (DDR) => banks per layer
397 # devices per rank (DDR) => devices per layer ( 1 for HMC).
398 # The parameters for which no input is available are inherited from the DDR3
400 # This configuration includes the latencies from the DRAM to the logic layer of
402 class HMC_2500_x32(DDR3_1600_x64
):
404 # two banks per device with each bank 4MB [2]
407 # 1x32 configuration, 1 device with 32 TSVs [2]
408 device_bus_width
= 32
410 # HMC is a BL8 device [2]
413 # Each device has a page (row buffer) size of 256 bytes [2]
414 device_rowbuffer_size
= '256B'
416 # 1x32 configuration, so 1 device [2]
419 # 4 layers so 4 ranks [2]
420 ranks_per_channel
= 4
422 # HMC has 2 banks per layer [2]
423 # Each layer represents a rank. With 4 layers and 8 banks in total, each
424 # layer has 2 banks; thus 2 banks per rank.
430 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
433 # Values using DRAMSpec HMC model [1]
439 # tRRD depends on the power supply network for each vendor.
440 # We assume a tRRD of a double bank approach to be equal to 4 clock
441 # cycles (Assumption)
444 # activation limit is set to 0 since there are only 2 banks per vault layer.
447 # Values using DRAMSpec HMC model [1]
452 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz = 0.8
456 # Value using DRAMSpec HMC model [1]
459 # Set default controller parameters
460 page_policy
= 'close'
461 write_buffer_size
= 8
463 addr_mapping
= 'RoCoRaBaCh'
464 min_writes_per_switch
= 8
466 # A single DDR3-2133 x64 channel refining a selected subset of the
467 # options for the DDR-1600 configuration, based on the same DDR3-1600
468 # 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
469 # consistent across the two configurations.
470 class DDR3_2133_x64(DDR3_1600_x64
):
474 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
485 # Current values from datasheet
494 # A single DDR4-2400 x64 channel (one command and address bus), with
495 # timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
496 # in an 8x8 configuration.
497 class DDR4_2400_x64(DRAMCtrl
):
499 device_size
= '512MB'
501 # 8x8 configuration, 8 devices each with an 8-bit interface
504 # DDR4 is a BL8 device
507 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
508 device_rowbuffer_size
= '1kB'
510 # 8x8 configuration, so 8 devices
513 # Match our DDR3 configurations which is dual rank
514 ranks_per_channel
= 2
516 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
517 # Set to 4 for x4, x8 case
518 bank_groups_per_rank
= 4
520 # DDR4 has 16 banks (4 bank groups) in all
521 # configurations. Currently we do not capture the additional
522 # constraints incurred by the bank groups
525 # override the default buffer sizes and go for something larger to
526 # accommodate the larger bank count
527 write_buffer_size
= 128
528 read_buffer_size
= 64
533 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
534 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
535 # With bank group architectures, tBURST represents the CAS-to-CAS
536 # delay for bursts to different bank groups (tCCD_S)
539 # @2400 data rate, tCCD_L is 6 CK
540 # CAS-to-CAS delay for bursts to the same bank group
541 # tBURST is equivalent to tCCD_S; no explicit parameter required
542 # for CAS-to-CAS delay for bursts to different bank groups
551 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
554 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
563 # Here using the average of WTR_S and WTR_L
566 # Greater of 4 CK or 7.5 ns
569 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
572 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
575 # <=85C, half for >85C
578 # Current values from datasheet
590 # A single LPDDR2-S4 x32 interface (one command/address bus), with
591 # default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
592 # in a 1x32 configuration.
593 class LPDDR2_S4_1066_x32(DRAMCtrl
):
598 device_size
= '512MB'
600 # 1x32 configuration, 1 device with a 32-bit interface
601 device_bus_width
= 32
603 # LPDDR2_S4 is a BL4 and BL8 device
606 # Each device has a page (row buffer) size of 1KB
607 # (this depends on the memory density)
608 device_rowbuffer_size
= '1kB'
610 # 1x32 configuration, so 1 device
614 ranks_per_channel
= 1
616 # LPDDR2-S4 has 8 banks in all configurations
625 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
628 # Pre-charge one bank 15 ns (all banks 18 ns)
636 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
637 # Note this is a BL8 DDR device.
638 # Requests larger than 32 bytes are broken down into multiple requests
646 # Irrespective of speed grade, tWTR is 7.5 ns
649 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
652 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
655 # Activate to activate irrespective of density and speed grade
658 # Irrespective of density, tFAW is 50 ns
662 # Current values from datasheet
678 # A single WideIO x128 interface (one command and address bus), with
679 # default timings based on an estimated WIO-200 8 Gbit part.
680 class WideIO_200_x128(DRAMCtrl
):
685 device_size
= '1024MB'
687 # 1x128 configuration, 1 device with a 128-bit interface
688 device_bus_width
= 128
690 # This is a BL4 device
693 # Each device has a page (row buffer) size of 4KB
694 # (this depends on the memory density)
695 device_rowbuffer_size
= '4kB'
697 # 1x128 configuration, so 1 device
700 # Use one rank for a one-high die stack
701 ranks_per_channel
= 1
703 # WideIO has 4 banks in all configurations
715 # Read to precharge is same as the burst
718 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
719 # Note this is a BL4 SDR device.
725 # WIO 8 Gb, <=85C, half for >85C
728 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
731 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
734 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
737 # Activate to activate irrespective of density and speed grade
740 # Two instead of four activation window
744 # The WideIO specification does not provide current information
746 # A single LPDDR3 x32 interface (one command/address bus), with
747 # default timings based on a LPDDR3-1600 4 Gbit part (Micron
748 # EDF8132A1MC) in a 1x32 configuration.
749 class LPDDR3_1600_x32(DRAMCtrl
):
754 device_size
= '512MB'
756 # 1x32 configuration, 1 device with a 32-bit interface
757 device_bus_width
= 32
759 # LPDDR3 is a BL8 device
762 # Each device has a page (row buffer) size of 4KB
763 device_rowbuffer_size
= '4kB'
765 # 1x32 configuration, so 1 device
768 # Technically the datasheet is a dual-rank package, but for
769 # comparison with the LPDDR2 config we stick to a single rank
770 ranks_per_channel
= 1
772 # LPDDR3 has 8 banks in all configurations
780 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
786 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
789 # Pre-charge one bank 18 ns (all banks 21 ns)
792 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
793 # Note this is a BL8 DDR device.
794 # Requests larger than 32 bytes are broken down into multiple requests
802 # Irrespective of speed grade, tWTR is 7.5 ns
805 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
808 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
811 # Activate to activate irrespective of density and speed grade
814 # Irrespective of size, tFAW is 50 ns
818 # Current values from datasheet
834 # A single GDDR5 x64 interface, with
835 # default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
836 # H5GQ1H24AFR) in a 2x32 configuration.
837 class GDDR5_4000_x64(DRAMCtrl
):
839 device_size
= '128MB'
841 # 2x32 configuration, 1 device with a 32-bit interface
842 device_bus_width
= 32
844 # GDDR5 is a BL8 device
847 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
848 device_rowbuffer_size
= '256B'
850 # 2x32 configuration, so 2 devices
854 ranks_per_channel
= 1
856 # GDDR5 has 4 bank groups
857 bank_groups_per_rank
= 4
859 # GDDR5 has 16 banks with 4 bank groups
865 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
866 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
867 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
868 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
869 # With bank group architectures, tBURST represents the CAS-to-CAS
870 # delay for bursts to different bank groups (tCCD_S)
873 # @1000MHz data rate, tCCD_L is 3 CK
874 # CAS-to-CAS delay for bursts to the same bank group
875 # tBURST is equivalent to tCCD_S; no explicit parameter required
876 # for CAS-to-CAS delay for bursts to different bank groups
881 # tCL is not directly found in datasheet and assumed equal tRCD
887 # RRD_S (different bank group)
888 # RRD_S is 5.5 ns in datasheet.
889 # rounded to the next multiple of tCK
892 # RRD_L (same bank group)
893 # RRD_L is 5.5 ns in datasheet.
894 # rounded to the next multiple of tCK
900 # Therefore, activation limit is set to 0
906 # Here using the average of WTR_S and WTR_L
909 # Read-to-Precharge 2 CK
915 # A single HBM x128 interface (one command and address bus), with
916 # default timings based on data publically released
917 # ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
918 # IDD measurement values, and by extrapolating data from other classes.
919 # Architecture values based on published HBM spec
920 # A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
921 class HBM_1000_4H_x128(DRAMCtrl
):
922 # HBM gen1 supports up to 8 128-bit physical channels
923 # Configuration defines a single channel, with the capacity
924 # set to (full_ stack_capacity / 8) based on 2Gb dies
925 # To use all 8 channels, set 'channels' parameter to 8 in
926 # system configuration
928 # 128-bit interface legacy mode
929 device_bus_width
= 128
931 # HBM supports BL4 and BL2 (legacy mode only)
934 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
935 # with 8 channels, 128MB per channel
936 device_size
= '128MB'
938 device_rowbuffer_size
= '2kB'
940 # 1x128 configuration
943 # HBM does not have a CS pin; set rank to 1
944 ranks_per_channel
= 1
946 # HBM has 8 or 16 banks depending on capacity
947 # 2Gb dies have 8 banks
950 # depending on frequency, bank groups may be required
951 # will always have 4 bank groups when enabled
952 # current specifications do not define the minimum frequency for
953 # bank group architecture
954 # setting bank_groups_per_rank to 0 to disable until range is defined
955 bank_groups_per_rank
= 0
957 # 500 MHz for 1Gbps DDR data rate
960 # use values from IDD measurement in JEDEC spec
961 # use tRP value for tRCD and tCL similar to other classes
967 # BL2 and BL4 supported, default to BL4
968 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
971 # value for 2Gb device from JEDEC spec
974 # value for 2Gb device from JEDEC spec
977 # extrapolate the following from LPDDR configs, using ns values
978 # to minimize burst length, prefetch differences
983 # start with 2 cycles turnaround, similar to other memory classes
984 # could be more with variations across the stack
987 # single rank device, set to 0
990 # from MemCon example, tRRD is 4ns with 2ns tCK
993 # from MemCon example, tFAW is 30ns with 2ns tCK
1000 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1003 # A single HBM x64 interface (one command and address bus), with
1004 # default timings based on HBM gen1 and data publically released
1005 # A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1006 # Note: This defines a pseudo-channel with a unique controller
1007 # instantiated per pseudo-channel
1008 # Stay at same IO rate (1Gbps) to maintain timing relationship with
1009 # HBM gen1 class (HBM_1000_4H_x128) where possible
1010 class HBM_1000_4H_x64(HBM_1000_4H_x128
):
1011 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1012 # Configuration defines a single pseudo channel, with the capacity
1013 # set to (full_ stack_capacity / 16) based on 8Gb dies
1014 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1015 # system configuration
1017 # 64-bit pseudo-channle interface
1018 device_bus_width
= 64
1020 # HBM pseudo-channel only supports BL4
1023 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1024 # with 16 channels, 256MB per channel
1025 device_size
= '256MB'
1027 # page size is halved with pseudo-channel; maintaining the same same number
1028 # of rows per pseudo-channel with 2X banks across 2 channels
1029 device_rowbuffer_size
= '1kB'
1031 # HBM has 8 or 16 banks depending on capacity
1032 # Starting with 4Gb dies, 16 banks are defined
1035 # reset tRFC for larger, 8Gb device
1036 # use HBM1 4Gb value as a starting point
1039 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1041 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns