1 # Copyright (c) 2012-2014 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2013 Amin Farmahini-Farahani
14 # Copyright (c) 2015 University of Kaiserslautern
15 # Copyright (c) 2015 The University of Bologna
16 # All rights reserved.
18 # Redistribution and use in source and binary forms, with or without
19 # modification, are permitted provided that the following conditions are
20 # met: redistributions of source code must retain the above copyright
21 # notice, this list of conditions and the following disclaimer;
22 # redistributions in binary form must reproduce the above copyright
23 # notice, this list of conditions and the following disclaimer in the
24 # documentation and/or other materials provided with the distribution;
25 # neither the name of the copyright holders nor the names of its
26 # contributors may be used to endorse or promote products derived from
27 # this software without specific prior written permission.
29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 # Authors: Andreas Hansson
47 from m5
.params
import *
48 from AbstractMemory
import *
50 # Enum for memory scheduling algorithms, currently First-Come
51 # First-Served and a First-Row Hit then First-Come First-Served
52 class MemSched(Enum
): vals
= ['fcfs', 'frfcfs']
54 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
55 # channel, rank, bank, row and column, respectively, and going from
56 # MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
57 # suitable for an open-page policy, optimising for sequential accesses
58 # hitting in the open row. For a closed-page policy, RoCoRaBaCh
59 # maximises parallelism.
60 class AddrMap(Enum
): vals
= ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
62 # Enum for the page policy, either open, open_adaptive, close, or
64 class PageManage(Enum
): vals
= ['open', 'open_adaptive', 'close',
67 # DRAMCtrl is a single-channel single-ported DRAM controller model
68 # that aims to model the most important system-level performance
69 # effects of a DRAM without getting into too much detail of the DRAM
71 class DRAMCtrl(AbstractMemory
):
73 cxx_header
= "mem/dram_ctrl.hh"
75 # single-ported on the system interface side, instantiate with a
76 # bus in front of the controller for multiple ports
77 port
= SlavePort("Slave port")
79 # the basic configuration of the controller architecture, note
80 # that each entry corresponds to a burst for the specific DRAM
81 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
82 # the cacheline size or request/packet size
83 write_buffer_size
= Param
.Unsigned(64, "Number of write queue entries")
84 read_buffer_size
= Param
.Unsigned(32, "Number of read queue entries")
86 # threshold in percent for when to forcefully trigger writes and
87 # start emptying the write buffer
88 write_high_thresh_perc
= Param
.Percent(85, "Threshold to force writes")
90 # threshold in percentage for when to start writes if the read
92 write_low_thresh_perc
= Param
.Percent(50, "Threshold to start writes")
94 # minimum write bursts to schedule before switching back to reads
95 min_writes_per_switch
= Param
.Unsigned(16, "Minimum write bursts before "
98 # scheduler, address map and page policy
99 mem_sched_policy
= Param
.MemSched('frfcfs', "Memory scheduling policy")
100 addr_mapping
= Param
.AddrMap('RoRaBaCoCh', "Address mapping policy")
101 page_policy
= Param
.PageManage('open_adaptive', "Page management policy")
103 # enforce a limit on the number of accesses per row
104 max_accesses_per_row
= Param
.Unsigned(16, "Max accesses per row before "
107 # size of DRAM Chip in Bytes
108 device_size
= Param
.MemorySize("Size of DRAM chip")
110 # pipeline latency of the controller and PHY, split into a
111 # frontend part and a backend part, with reads and writes serviced
112 # by the queues only seeing the frontend contribution, and reads
113 # serviced by the memory seeing the sum of the two
114 static_frontend_latency
= Param
.Latency("10ns", "Static frontend latency")
115 static_backend_latency
= Param
.Latency("10ns", "Static backend latency")
117 # the physical organisation of the DRAM
118 device_bus_width
= Param
.Unsigned("data bus width in bits for each DRAM "\
120 burst_length
= Param
.Unsigned("Burst lenght (BL) in beats")
121 device_rowbuffer_size
= Param
.MemorySize("Page (row buffer) size per "\
123 devices_per_rank
= Param
.Unsigned("Number of devices/chips per rank")
124 ranks_per_channel
= Param
.Unsigned("Number of ranks per channel")
126 # default to 0 bank groups per rank, indicating bank group architecture
128 # update per memory class when bank group architecture is supported
129 bank_groups_per_rank
= Param
.Unsigned(0, "Number of bank groups per rank")
130 banks_per_rank
= Param
.Unsigned("Number of banks per rank")
131 # only used for the address mapping as the controller by
132 # construction is a single channel and multiple controllers have
133 # to be instantiated for a multi-channel configuration
134 channels
= Param
.Unsigned(1, "Number of channels")
136 # For power modelling we need to know if the DRAM has a DLL or not
137 dll
= Param
.Bool(True, "DRAM has DLL or not")
139 # DRAMPower provides in addition to the core power, the possibility to
140 # include RD/WR termination and IO power. This calculation assumes some
141 # default values. The integration of DRAMPower with gem5 does not include
142 # IO and RD/WR termination power by default. This might be added as an
143 # additional feature in the future.
145 # timing behaviour and constraints - all in nanoseconds
147 # the base clock period of the DRAM
148 tCK
= Param
.Latency("Clock period")
150 # the amount of time in nanoseconds from issuing an activate command
151 # to the data being available in the row buffer for a read/write
152 tRCD
= Param
.Latency("RAS to CAS delay")
154 # the time from issuing a read/write command to seeing the actual data
155 tCL
= Param
.Latency("CAS latency")
157 # minimum time between a precharge and subsequent activate
158 tRP
= Param
.Latency("Row precharge time")
160 # minimum time between an activate and a precharge to the same row
161 tRAS
= Param
.Latency("ACT to PRE delay")
163 # minimum time between a write data transfer and a precharge
164 tWR
= Param
.Latency("Write recovery time")
166 # minimum time between a read and precharge command
167 tRTP
= Param
.Latency("Read to precharge")
169 # time to complete a burst transfer, typically the burst length
170 # divided by two due to the DDR bus, but by making it a parameter
171 # it is easier to also evaluate SDR memories like WideIO.
172 # This parameter has to account for burst length.
173 # Read/Write requests with data size larger than one full burst are broken
174 # down into multiple requests in the controller
175 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
176 # With bank group architectures, tBURST represents the CAS-to-CAS
177 # delay for bursts to different bank groups (tCCD_S)
178 tBURST
= Param
.Latency("Burst duration (for DDR burst length / 2 cycles)")
180 # CAS-to-CAS delay for bursts to the same bank group
181 # only utilized with bank group architectures; set to 0 for default case
182 # tBURST is equivalent to tCCD_S; no explicit parameter required
183 # for CAS-to-CAS delay for bursts to different bank groups
184 tCCD_L
= Param
.Latency("0ns", "Same bank group CAS to CAS delay")
186 # time taken to complete one refresh cycle (N rows in all banks)
187 tRFC
= Param
.Latency("Refresh cycle time")
189 # refresh command interval, how often a "ref" command needs
190 # to be sent. It is 7.8 us for a 64ms refresh requirement
191 tREFI
= Param
.Latency("Refresh command interval")
193 # write-to-read, same rank turnaround penalty
194 tWTR
= Param
.Latency("Write to read, same rank switching time")
196 # read-to-write, same rank turnaround penalty
197 tRTW
= Param
.Latency("Read to write, same rank switching time")
199 # rank-to-rank bus delay penalty
200 # this does not correlate to a memory timing parameter and encompasses:
201 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
202 # different rank bus delay
203 tCS
= Param
.Latency("Rank to rank switching time")
205 # minimum row activate to row activate delay time
206 tRRD
= Param
.Latency("ACT to ACT delay")
208 # only utilized with bank group architectures; set to 0 for default case
209 tRRD_L
= Param
.Latency("0ns", "Same bank group ACT to ACT delay")
211 # time window in which a maximum number of activates are allowed
212 # to take place, set to 0 to disable
213 tXAW
= Param
.Latency("X activation window")
214 activation_limit
= Param
.Unsigned("Max number of activates in window")
216 # time to exit power-down mode
217 # Exit power-down to next valid command delay
218 tXP
= Param
.Latency("0ns", "Power-up Delay")
220 # Exit Powerdown to commands requiring a locked DLL
221 tXPDLL
= Param
.Latency("0ns", "Power-up Delay with locked DLL")
223 # time to exit self-refresh mode
224 tXS
= Param
.Latency("0ns", "Self-refresh exit latency")
226 # time to exit self-refresh mode with locked DLL
227 tXSDLL
= Param
.Latency("0ns", "Self-refresh exit latency DLL")
229 # Currently rolled into other params
230 ######################################################################
232 # tRC - assumed to be tRAS + tRP
234 # Power Behaviour and Constraints
235 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
236 # defined as VDD and VDD2. Each current is defined for each voltage domain
237 # separately. For example, current IDD0 is active-precharge current for
238 # voltage domain VDD and current IDD02 is active-precharge current for
239 # voltage domain VDD2.
240 # By default all currents are set to 0mA. Users who are only interested in
241 # the performance of DRAMs can leave them at 0.
243 # Operating 1 Bank Active-Precharge current
244 IDD0
= Param
.Current("0mA", "Active precharge current")
246 # Operating 1 Bank Active-Precharge current multiple voltage Range
247 IDD02
= Param
.Current("0mA", "Active precharge current VDD2")
249 # Precharge Power-down Current: Slow exit
250 IDD2P0
= Param
.Current("0mA", "Precharge Powerdown slow")
252 # Precharge Power-down Current: Slow exit multiple voltage Range
253 IDD2P02
= Param
.Current("0mA", "Precharge Powerdown slow VDD2")
255 # Precharge Power-down Current: Fast exit
256 IDD2P1
= Param
.Current("0mA", "Precharge Powerdown fast")
258 # Precharge Power-down Current: Fast exit multiple voltage Range
259 IDD2P12
= Param
.Current("0mA", "Precharge Powerdown fast VDD2")
261 # Precharge Standby current
262 IDD2N
= Param
.Current("0mA", "Precharge Standby current")
264 # Precharge Standby current multiple voltage range
265 IDD2N2
= Param
.Current("0mA", "Precharge Standby current VDD2")
267 # Active Power-down current: slow exit
268 IDD3P0
= Param
.Current("0mA", "Active Powerdown slow")
270 # Active Power-down current: slow exit multiple voltage range
271 IDD3P02
= Param
.Current("0mA", "Active Powerdown slow VDD2")
273 # Active Power-down current : fast exit
274 IDD3P1
= Param
.Current("0mA", "Active Powerdown fast")
276 # Active Power-down current : fast exit multiple voltage range
277 IDD3P12
= Param
.Current("0mA", "Active Powerdown fast VDD2")
279 # Active Standby current
280 IDD3N
= Param
.Current("0mA", "Active Standby current")
282 # Active Standby current multiple voltage range
283 IDD3N2
= Param
.Current("0mA", "Active Standby current VDD2")
285 # Burst Read Operating Current
286 IDD4R
= Param
.Current("0mA", "READ current")
288 # Burst Read Operating Current multiple voltage range
289 IDD4R2
= Param
.Current("0mA", "READ current VDD2")
291 # Burst Write Operating Current
292 IDD4W
= Param
.Current("0mA", "WRITE current")
294 # Burst Write Operating Current multiple voltage range
295 IDD4W2
= Param
.Current("0mA", "WRITE current VDD2")
298 IDD5
= Param
.Current("0mA", "Refresh current")
300 # Refresh Current multiple voltage range
301 IDD52
= Param
.Current("0mA", "Refresh current VDD2")
303 # Self-Refresh Current
304 IDD6
= Param
.Current("0mA", "Self-refresh Current")
306 # Self-Refresh Current multiple voltage range
307 IDD62
= Param
.Current("0mA", "Self-refresh Current VDD2")
309 # Main voltage range of the DRAM
310 VDD
= Param
.Voltage("0V", "Main Voltage Range")
312 # Second voltage range defined by some DRAMs
313 VDD2
= Param
.Voltage("0V", "2nd Voltage Range")
315 # A single DDR3-1600 x64 channel (one command and address bus), with
316 # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
317 # an 8x8 configuration.
318 class DDR3_1600_x64(DRAMCtrl
):
319 # size of device in bytes
320 device_size
= '512MB'
322 # 8x8 configuration, 8 devices each with an 8-bit interface
325 # DDR3 is a BL8 device
328 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
329 device_rowbuffer_size
= '1kB'
331 # 8x8 configuration, so 8 devices
335 ranks_per_channel
= 2
337 # DDR3 has 8 banks in all configurations
343 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
358 # Greater of 4 CK or 7.5 ns
361 # Greater of 4 CK or 7.5 ns
364 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
367 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
370 # <=85C, half for >85C
373 # Current values from datasheet
382 # A single HMC-2500 x32 model based on:
383 # [1] DRAMSpec: a high-level DRAM bank modelling tool
384 # developed at the University of Kaiserslautern. This high level tool
385 # uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
386 # estimate the DRAM bank latency and power numbers.
387 # [2] High performance AXI-4.0 based interconnect for extensible smart memory
388 # cubes (E. Azarkhish et. al)
389 # Assumed for the HMC model is a 30 nm technology node.
390 # The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
392 # Each layer has 16 vaults and each vault consists of 2 banks per layer.
393 # In order to be able to use the same controller used for 2D DRAM generations
394 # for HMC, the following analogy is done:
395 # Channel (DDR) => Vault (HMC)
396 # device_size (DDR) => size of a single layer in a vault
397 # ranks per channel (DDR) => number of layers
398 # banks per rank (DDR) => banks per layer
399 # devices per rank (DDR) => devices per layer ( 1 for HMC).
400 # The parameters for which no input is available are inherited from the DDR3
402 # This configuration includes the latencies from the DRAM to the logic layer
404 class HMC_2500_x32(DDR3_1600_x64
):
406 # two banks per device with each bank 4MB [2]
409 # 1x32 configuration, 1 device with 32 TSVs [2]
410 device_bus_width
= 32
412 # HMC is a BL8 device [2]
415 # Each device has a page (row buffer) size of 256 bytes [2]
416 device_rowbuffer_size
= '256B'
418 # 1x32 configuration, so 1 device [2]
421 # 4 layers so 4 ranks [2]
422 ranks_per_channel
= 4
424 # HMC has 2 banks per layer [2]
425 # Each layer represents a rank. With 4 layers and 8 banks in total, each
426 # layer has 2 banks; thus 2 banks per rank.
432 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
435 # Values using DRAMSpec HMC model [1]
441 # tRRD depends on the power supply network for each vendor.
442 # We assume a tRRD of a double bank approach to be equal to 4 clock
443 # cycles (Assumption)
446 # activation limit is set to 0 since there are only 2 banks per vault
450 # Values using DRAMSpec HMC model [1]
455 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
456 # 0.8 ns (Assumption)
459 # Value using DRAMSpec HMC model [1]
462 # The default page policy in the vault controllers is simple closed page
463 # [2] nevertheless 'close' policy opens and closes the row multiple times
464 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
465 page_policy
= 'close_adaptive'
467 # RoCoRaBaCh resembles the default address mapping in HMC
468 addr_mapping
= 'RoCoRaBaCh'
469 min_writes_per_switch
= 8
471 # These parameters do not directly correlate with buffer_size in real
472 # hardware. Nevertheless, their value has been tuned to achieve a
473 # bandwidth similar to the cycle-accurate model in [2]
474 write_buffer_size
= 32
475 read_buffer_size
= 32
477 # The static latency of the vault controllers is estimated to be smaller
478 # than a full DRAM channel controller
479 static_backend_latency
='4ns'
480 static_frontend_latency
='4ns'
482 # A single DDR3-2133 x64 channel refining a selected subset of the
483 # options for the DDR-1600 configuration, based on the same DDR3-1600
484 # 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
485 # consistent across the two configurations.
486 class DDR3_2133_x64(DDR3_1600_x64
):
490 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
501 # Current values from datasheet
510 # A single DDR4-2400 x64 channel (one command and address bus), with
511 # timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
512 # in an 8x8 configuration.
513 class DDR4_2400_x64(DRAMCtrl
):
515 device_size
= '512MB'
517 # 8x8 configuration, 8 devices each with an 8-bit interface
520 # DDR4 is a BL8 device
523 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
524 device_rowbuffer_size
= '1kB'
526 # 8x8 configuration, so 8 devices
529 # Match our DDR3 configurations which is dual rank
530 ranks_per_channel
= 2
532 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
533 # Set to 4 for x4, x8 case
534 bank_groups_per_rank
= 4
536 # DDR4 has 16 banks (4 bank groups) in all
537 # configurations. Currently we do not capture the additional
538 # constraints incurred by the bank groups
541 # override the default buffer sizes and go for something larger to
542 # accommodate the larger bank count
543 write_buffer_size
= 128
544 read_buffer_size
= 64
549 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
550 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
551 # With bank group architectures, tBURST represents the CAS-to-CAS
552 # delay for bursts to different bank groups (tCCD_S)
555 # @2400 data rate, tCCD_L is 6 CK
556 # CAS-to-CAS delay for bursts to the same bank group
557 # tBURST is equivalent to tCCD_S; no explicit parameter required
558 # for CAS-to-CAS delay for bursts to different bank groups
567 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
570 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
579 # Here using the average of WTR_S and WTR_L
582 # Greater of 4 CK or 7.5 ns
585 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
588 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
591 # <=85C, half for >85C
594 # Current values from datasheet
606 # A single LPDDR2-S4 x32 interface (one command/address bus), with
607 # default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
608 # in a 1x32 configuration.
609 class LPDDR2_S4_1066_x32(DRAMCtrl
):
614 device_size
= '512MB'
616 # 1x32 configuration, 1 device with a 32-bit interface
617 device_bus_width
= 32
619 # LPDDR2_S4 is a BL4 and BL8 device
622 # Each device has a page (row buffer) size of 1KB
623 # (this depends on the memory density)
624 device_rowbuffer_size
= '1kB'
626 # 1x32 configuration, so 1 device
630 ranks_per_channel
= 1
632 # LPDDR2-S4 has 8 banks in all configurations
641 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
644 # Pre-charge one bank 15 ns (all banks 18 ns)
652 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
653 # Note this is a BL8 DDR device.
654 # Requests larger than 32 bytes are broken down into multiple requests
662 # Irrespective of speed grade, tWTR is 7.5 ns
665 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
668 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
671 # Activate to activate irrespective of density and speed grade
674 # Irrespective of density, tFAW is 50 ns
678 # Current values from datasheet
694 # A single WideIO x128 interface (one command and address bus), with
695 # default timings based on an estimated WIO-200 8 Gbit part.
696 class WideIO_200_x128(DRAMCtrl
):
701 device_size
= '1024MB'
703 # 1x128 configuration, 1 device with a 128-bit interface
704 device_bus_width
= 128
706 # This is a BL4 device
709 # Each device has a page (row buffer) size of 4KB
710 # (this depends on the memory density)
711 device_rowbuffer_size
= '4kB'
713 # 1x128 configuration, so 1 device
716 # Use one rank for a one-high die stack
717 ranks_per_channel
= 1
719 # WideIO has 4 banks in all configurations
731 # Read to precharge is same as the burst
734 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
735 # Note this is a BL4 SDR device.
741 # WIO 8 Gb, <=85C, half for >85C
744 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
747 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
750 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
753 # Activate to activate irrespective of density and speed grade
756 # Two instead of four activation window
760 # The WideIO specification does not provide current information
762 # A single LPDDR3 x32 interface (one command/address bus), with
763 # default timings based on a LPDDR3-1600 4 Gbit part (Micron
764 # EDF8132A1MC) in a 1x32 configuration.
765 class LPDDR3_1600_x32(DRAMCtrl
):
770 device_size
= '512MB'
772 # 1x32 configuration, 1 device with a 32-bit interface
773 device_bus_width
= 32
775 # LPDDR3 is a BL8 device
778 # Each device has a page (row buffer) size of 4KB
779 device_rowbuffer_size
= '4kB'
781 # 1x32 configuration, so 1 device
784 # Technically the datasheet is a dual-rank package, but for
785 # comparison with the LPDDR2 config we stick to a single rank
786 ranks_per_channel
= 1
788 # LPDDR3 has 8 banks in all configurations
796 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
802 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
805 # Pre-charge one bank 18 ns (all banks 21 ns)
808 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
809 # Note this is a BL8 DDR device.
810 # Requests larger than 32 bytes are broken down into multiple requests
818 # Irrespective of speed grade, tWTR is 7.5 ns
821 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
824 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
827 # Activate to activate irrespective of density and speed grade
830 # Irrespective of size, tFAW is 50 ns
834 # Current values from datasheet
850 # A single GDDR5 x64 interface, with
851 # default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
852 # H5GQ1H24AFR) in a 2x32 configuration.
853 class GDDR5_4000_x64(DRAMCtrl
):
855 device_size
= '128MB'
857 # 2x32 configuration, 1 device with a 32-bit interface
858 device_bus_width
= 32
860 # GDDR5 is a BL8 device
863 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
864 device_rowbuffer_size
= '256B'
866 # 2x32 configuration, so 2 devices
870 ranks_per_channel
= 1
872 # GDDR5 has 4 bank groups
873 bank_groups_per_rank
= 4
875 # GDDR5 has 16 banks with 4 bank groups
881 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
882 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
883 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
884 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
885 # With bank group architectures, tBURST represents the CAS-to-CAS
886 # delay for bursts to different bank groups (tCCD_S)
889 # @1000MHz data rate, tCCD_L is 3 CK
890 # CAS-to-CAS delay for bursts to the same bank group
891 # tBURST is equivalent to tCCD_S; no explicit parameter required
892 # for CAS-to-CAS delay for bursts to different bank groups
897 # tCL is not directly found in datasheet and assumed equal tRCD
903 # RRD_S (different bank group)
904 # RRD_S is 5.5 ns in datasheet.
905 # rounded to the next multiple of tCK
908 # RRD_L (same bank group)
909 # RRD_L is 5.5 ns in datasheet.
910 # rounded to the next multiple of tCK
916 # Therefore, activation limit is set to 0
922 # Here using the average of WTR_S and WTR_L
925 # Read-to-Precharge 2 CK
931 # A single HBM x128 interface (one command and address bus), with
932 # default timings based on data publically released
933 # ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
934 # IDD measurement values, and by extrapolating data from other classes.
935 # Architecture values based on published HBM spec
936 # A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
937 class HBM_1000_4H_x128(DRAMCtrl
):
938 # HBM gen1 supports up to 8 128-bit physical channels
939 # Configuration defines a single channel, with the capacity
940 # set to (full_ stack_capacity / 8) based on 2Gb dies
941 # To use all 8 channels, set 'channels' parameter to 8 in
942 # system configuration
944 # 128-bit interface legacy mode
945 device_bus_width
= 128
947 # HBM supports BL4 and BL2 (legacy mode only)
950 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
951 # with 8 channels, 128MB per channel
952 device_size
= '128MB'
954 device_rowbuffer_size
= '2kB'
956 # 1x128 configuration
959 # HBM does not have a CS pin; set rank to 1
960 ranks_per_channel
= 1
962 # HBM has 8 or 16 banks depending on capacity
963 # 2Gb dies have 8 banks
966 # depending on frequency, bank groups may be required
967 # will always have 4 bank groups when enabled
968 # current specifications do not define the minimum frequency for
969 # bank group architecture
970 # setting bank_groups_per_rank to 0 to disable until range is defined
971 bank_groups_per_rank
= 0
973 # 500 MHz for 1Gbps DDR data rate
976 # use values from IDD measurement in JEDEC spec
977 # use tRP value for tRCD and tCL similar to other classes
983 # BL2 and BL4 supported, default to BL4
984 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
987 # value for 2Gb device from JEDEC spec
990 # value for 2Gb device from JEDEC spec
993 # extrapolate the following from LPDDR configs, using ns values
994 # to minimize burst length, prefetch differences
999 # start with 2 cycles turnaround, similar to other memory classes
1000 # could be more with variations across the stack
1003 # single rank device, set to 0
1006 # from MemCon example, tRRD is 4ns with 2ns tCK
1009 # from MemCon example, tFAW is 30ns with 2ns tCK
1011 activation_limit
= 4
1016 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1019 # A single HBM x64 interface (one command and address bus), with
1020 # default timings based on HBM gen1 and data publically released
1021 # A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1022 # Note: This defines a pseudo-channel with a unique controller
1023 # instantiated per pseudo-channel
1024 # Stay at same IO rate (1Gbps) to maintain timing relationship with
1025 # HBM gen1 class (HBM_1000_4H_x128) where possible
1026 class HBM_1000_4H_x64(HBM_1000_4H_x128
):
1027 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1028 # Configuration defines a single pseudo channel, with the capacity
1029 # set to (full_ stack_capacity / 16) based on 8Gb dies
1030 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1031 # system configuration
1033 # 64-bit pseudo-channle interface
1034 device_bus_width
= 64
1036 # HBM pseudo-channel only supports BL4
1039 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1040 # with 16 channels, 256MB per channel
1041 device_size
= '256MB'
1043 # page size is halved with pseudo-channel; maintaining the same same number
1044 # of rows per pseudo-channel with 2X banks across 2 channels
1045 device_rowbuffer_size
= '1kB'
1047 # HBM has 8 or 16 banks depending on capacity
1048 # Starting with 4Gb dies, 16 banks are defined
1051 # reset tRFC for larger, 8Gb device
1052 # use HBM1 4Gb value as a starting point
1055 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1057 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns