1 # Copyright (c) 2012-2018 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2013 Amin Farmahini-Farahani
14 # Copyright (c) 2015 University of Kaiserslautern
15 # Copyright (c) 2015 The University of Bologna
16 # All rights reserved.
18 # Redistribution and use in source and binary forms, with or without
19 # modification, are permitted provided that the following conditions are
20 # met: redistributions of source code must retain the above copyright
21 # notice, this list of conditions and the following disclaimer;
22 # redistributions in binary form must reproduce the above copyright
23 # notice, this list of conditions and the following disclaimer in the
24 # documentation and/or other materials provided with the distribution;
25 # neither the name of the copyright holders nor the names of its
26 # contributors may be used to endorse or promote products derived from
27 # this software without specific prior written permission.
29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 # Authors: Andreas Hansson
47 from m5
.params
import *
48 from m5
.proxy
import *
49 from AbstractMemory
import *
51 # Enum for memory scheduling algorithms, currently First-Come
52 # First-Served and a First-Row Hit then First-Come First-Served
53 class MemSched(Enum
): vals
= ['fcfs', 'frfcfs']
55 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
56 # channel, rank, bank, row and column, respectively, and going from
57 # MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
58 # suitable for an open-page policy, optimising for sequential accesses
59 # hitting in the open row. For a closed-page policy, RoCoRaBaCh
60 # maximises parallelism.
61 class AddrMap(Enum
): vals
= ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
63 # Enum for the page policy, either open, open_adaptive, close, or
65 class PageManage(Enum
): vals
= ['open', 'open_adaptive', 'close',
68 # DRAMCtrl is a single-channel single-ported DRAM controller model
69 # that aims to model the most important system-level performance
70 # effects of a DRAM without getting into too much detail of the DRAM
72 class DRAMCtrl(AbstractMemory
):
74 cxx_header
= "mem/dram_ctrl.hh"
76 # single-ported on the system interface side, instantiate with a
77 # bus in front of the controller for multiple ports
78 port
= SlavePort("Slave port")
80 # the basic configuration of the controller architecture, note
81 # that each entry corresponds to a burst for the specific DRAM
82 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
83 # the cacheline size or request/packet size
84 write_buffer_size
= Param
.Unsigned(64, "Number of write queue entries")
85 read_buffer_size
= Param
.Unsigned(32, "Number of read queue entries")
87 # threshold in percent for when to forcefully trigger writes and
88 # start emptying the write buffer
89 write_high_thresh_perc
= Param
.Percent(85, "Threshold to force writes")
91 # threshold in percentage for when to start writes if the read
93 write_low_thresh_perc
= Param
.Percent(50, "Threshold to start writes")
95 # minimum write bursts to schedule before switching back to reads
96 min_writes_per_switch
= Param
.Unsigned(16, "Minimum write bursts before "
99 # scheduler, address map and page policy
100 mem_sched_policy
= Param
.MemSched('frfcfs', "Memory scheduling policy")
101 addr_mapping
= Param
.AddrMap('RoRaBaCoCh', "Address mapping policy")
102 page_policy
= Param
.PageManage('open_adaptive', "Page management policy")
104 # enforce a limit on the number of accesses per row
105 max_accesses_per_row
= Param
.Unsigned(16, "Max accesses per row before "
108 # size of DRAM Chip in Bytes
109 device_size
= Param
.MemorySize("Size of DRAM chip")
111 # pipeline latency of the controller and PHY, split into a
112 # frontend part and a backend part, with reads and writes serviced
113 # by the queues only seeing the frontend contribution, and reads
114 # serviced by the memory seeing the sum of the two
115 static_frontend_latency
= Param
.Latency("10ns", "Static frontend latency")
116 static_backend_latency
= Param
.Latency("10ns", "Static backend latency")
118 # the physical organisation of the DRAM
119 device_bus_width
= Param
.Unsigned("data bus width in bits for each DRAM "\
121 burst_length
= Param
.Unsigned("Burst lenght (BL) in beats")
122 device_rowbuffer_size
= Param
.MemorySize("Page (row buffer) size per "\
124 devices_per_rank
= Param
.Unsigned("Number of devices/chips per rank")
125 ranks_per_channel
= Param
.Unsigned("Number of ranks per channel")
127 # default to 0 bank groups per rank, indicating bank group architecture
129 # update per memory class when bank group architecture is supported
130 bank_groups_per_rank
= Param
.Unsigned(0, "Number of bank groups per rank")
131 banks_per_rank
= Param
.Unsigned("Number of banks per rank")
132 # only used for the address mapping as the controller by
133 # construction is a single channel and multiple controllers have
134 # to be instantiated for a multi-channel configuration
135 channels
= Param
.Unsigned(1, "Number of channels")
137 # For power modelling we need to know if the DRAM has a DLL or not
138 dll
= Param
.Bool(True, "DRAM has DLL or not")
140 # DRAMPower provides in addition to the core power, the possibility to
141 # include RD/WR termination and IO power. This calculation assumes some
142 # default values. The integration of DRAMPower with gem5 does not include
143 # IO and RD/WR termination power by default. This might be added as an
144 # additional feature in the future.
146 # timing behaviour and constraints - all in nanoseconds
148 # the base clock period of the DRAM
149 tCK
= Param
.Latency("Clock period")
151 # the amount of time in nanoseconds from issuing an activate command
152 # to the data being available in the row buffer for a read/write
153 tRCD
= Param
.Latency("RAS to CAS delay")
155 # the time from issuing a read/write command to seeing the actual data
156 tCL
= Param
.Latency("CAS latency")
158 # minimum time between a precharge and subsequent activate
159 tRP
= Param
.Latency("Row precharge time")
161 # minimum time between an activate and a precharge to the same row
162 tRAS
= Param
.Latency("ACT to PRE delay")
164 # minimum time between a write data transfer and a precharge
165 tWR
= Param
.Latency("Write recovery time")
167 # minimum time between a read and precharge command
168 tRTP
= Param
.Latency("Read to precharge")
170 # time to complete a burst transfer, typically the burst length
171 # divided by two due to the DDR bus, but by making it a parameter
172 # it is easier to also evaluate SDR memories like WideIO.
173 # This parameter has to account for burst length.
174 # Read/Write requests with data size larger than one full burst are broken
175 # down into multiple requests in the controller
176 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
177 # With bank group architectures, tBURST represents the CAS-to-CAS
178 # delay for bursts to different bank groups (tCCD_S)
179 tBURST
= Param
.Latency("Burst duration (for DDR burst length / 2 cycles)")
181 # CAS-to-CAS delay for bursts to the same bank group
182 # only utilized with bank group architectures; set to 0 for default case
183 # tBURST is equivalent to tCCD_S; no explicit parameter required
184 # for CAS-to-CAS delay for bursts to different bank groups
185 tCCD_L
= Param
.Latency("0ns", "Same bank group CAS to CAS delay")
187 # Write-to-Write delay for bursts to the same bank group
188 # only utilized with bank group architectures; set to 0 for default case
189 # This will be used to enable different same bank group delays
190 # for writes versus reads
191 tCCD_L_WR
= Param
.Latency(Self
.tCCD_L
,
192 "Same bank group Write to Write delay")
194 # time taken to complete one refresh cycle (N rows in all banks)
195 tRFC
= Param
.Latency("Refresh cycle time")
197 # refresh command interval, how often a "ref" command needs
198 # to be sent. It is 7.8 us for a 64ms refresh requirement
199 tREFI
= Param
.Latency("Refresh command interval")
201 # write-to-read, same rank turnaround penalty
202 tWTR
= Param
.Latency("Write to read, same rank switching time")
204 # read-to-write, same rank turnaround penalty
205 tRTW
= Param
.Latency("Read to write, same rank switching time")
207 # rank-to-rank bus delay penalty
208 # this does not correlate to a memory timing parameter and encompasses:
209 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
210 # different rank bus delay
211 tCS
= Param
.Latency("Rank to rank switching time")
213 # minimum row activate to row activate delay time
214 tRRD
= Param
.Latency("ACT to ACT delay")
216 # only utilized with bank group architectures; set to 0 for default case
217 tRRD_L
= Param
.Latency("0ns", "Same bank group ACT to ACT delay")
219 # time window in which a maximum number of activates are allowed
220 # to take place, set to 0 to disable
221 tXAW
= Param
.Latency("X activation window")
222 activation_limit
= Param
.Unsigned("Max number of activates in window")
224 # time to exit power-down mode
225 # Exit power-down to next valid command delay
226 tXP
= Param
.Latency("0ns", "Power-up Delay")
228 # Exit Powerdown to commands requiring a locked DLL
229 tXPDLL
= Param
.Latency("0ns", "Power-up Delay with locked DLL")
231 # time to exit self-refresh mode
232 tXS
= Param
.Latency("0ns", "Self-refresh exit latency")
234 # time to exit self-refresh mode with locked DLL
235 tXSDLL
= Param
.Latency("0ns", "Self-refresh exit latency DLL")
237 # Currently rolled into other params
238 ######################################################################
240 # tRC - assumed to be tRAS + tRP
242 # Power Behaviour and Constraints
243 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
244 # defined as VDD and VDD2. Each current is defined for each voltage domain
245 # separately. For example, current IDD0 is active-precharge current for
246 # voltage domain VDD and current IDD02 is active-precharge current for
247 # voltage domain VDD2.
248 # By default all currents are set to 0mA. Users who are only interested in
249 # the performance of DRAMs can leave them at 0.
251 # Operating 1 Bank Active-Precharge current
252 IDD0
= Param
.Current("0mA", "Active precharge current")
254 # Operating 1 Bank Active-Precharge current multiple voltage Range
255 IDD02
= Param
.Current("0mA", "Active precharge current VDD2")
257 # Precharge Power-down Current: Slow exit
258 IDD2P0
= Param
.Current("0mA", "Precharge Powerdown slow")
260 # Precharge Power-down Current: Slow exit multiple voltage Range
261 IDD2P02
= Param
.Current("0mA", "Precharge Powerdown slow VDD2")
263 # Precharge Power-down Current: Fast exit
264 IDD2P1
= Param
.Current("0mA", "Precharge Powerdown fast")
266 # Precharge Power-down Current: Fast exit multiple voltage Range
267 IDD2P12
= Param
.Current("0mA", "Precharge Powerdown fast VDD2")
269 # Precharge Standby current
270 IDD2N
= Param
.Current("0mA", "Precharge Standby current")
272 # Precharge Standby current multiple voltage range
273 IDD2N2
= Param
.Current("0mA", "Precharge Standby current VDD2")
275 # Active Power-down current: slow exit
276 IDD3P0
= Param
.Current("0mA", "Active Powerdown slow")
278 # Active Power-down current: slow exit multiple voltage range
279 IDD3P02
= Param
.Current("0mA", "Active Powerdown slow VDD2")
281 # Active Power-down current : fast exit
282 IDD3P1
= Param
.Current("0mA", "Active Powerdown fast")
284 # Active Power-down current : fast exit multiple voltage range
285 IDD3P12
= Param
.Current("0mA", "Active Powerdown fast VDD2")
287 # Active Standby current
288 IDD3N
= Param
.Current("0mA", "Active Standby current")
290 # Active Standby current multiple voltage range
291 IDD3N2
= Param
.Current("0mA", "Active Standby current VDD2")
293 # Burst Read Operating Current
294 IDD4R
= Param
.Current("0mA", "READ current")
296 # Burst Read Operating Current multiple voltage range
297 IDD4R2
= Param
.Current("0mA", "READ current VDD2")
299 # Burst Write Operating Current
300 IDD4W
= Param
.Current("0mA", "WRITE current")
302 # Burst Write Operating Current multiple voltage range
303 IDD4W2
= Param
.Current("0mA", "WRITE current VDD2")
306 IDD5
= Param
.Current("0mA", "Refresh current")
308 # Refresh Current multiple voltage range
309 IDD52
= Param
.Current("0mA", "Refresh current VDD2")
311 # Self-Refresh Current
312 IDD6
= Param
.Current("0mA", "Self-refresh Current")
314 # Self-Refresh Current multiple voltage range
315 IDD62
= Param
.Current("0mA", "Self-refresh Current VDD2")
317 # Main voltage range of the DRAM
318 VDD
= Param
.Voltage("0V", "Main Voltage Range")
320 # Second voltage range defined by some DRAMs
321 VDD2
= Param
.Voltage("0V", "2nd Voltage Range")
323 # A single DDR3-1600 x64 channel (one command and address bus), with
324 # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
325 # an 8x8 configuration.
326 class DDR3_1600_8x8(DRAMCtrl
):
327 # size of device in bytes
328 device_size
= '512MB'
330 # 8x8 configuration, 8 devices each with an 8-bit interface
333 # DDR3 is a BL8 device
336 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
337 device_rowbuffer_size
= '1kB'
339 # 8x8 configuration, so 8 devices
343 ranks_per_channel
= 2
345 # DDR3 has 8 banks in all configurations
351 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
366 # Greater of 4 CK or 7.5 ns
369 # Greater of 4 CK or 7.5 ns
372 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
375 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
378 # <=85C, half for >85C
381 # active powerdown and precharge powerdown exit time
384 # self refresh exit time
387 # Current values from datasheet Die Rev E,J
399 # A single HMC-2500 x32 model based on:
400 # [1] DRAMSpec: a high-level DRAM bank modelling tool
401 # developed at the University of Kaiserslautern. This high level tool
402 # uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
403 # estimate the DRAM bank latency and power numbers.
404 # [2] High performance AXI-4.0 based interconnect for extensible smart memory
405 # cubes (E. Azarkhish et. al)
406 # Assumed for the HMC model is a 30 nm technology node.
407 # The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
409 # Each layer has 16 vaults and each vault consists of 2 banks per layer.
410 # In order to be able to use the same controller used for 2D DRAM generations
411 # for HMC, the following analogy is done:
412 # Channel (DDR) => Vault (HMC)
413 # device_size (DDR) => size of a single layer in a vault
414 # ranks per channel (DDR) => number of layers
415 # banks per rank (DDR) => banks per layer
416 # devices per rank (DDR) => devices per layer ( 1 for HMC).
417 # The parameters for which no input is available are inherited from the DDR3
419 # This configuration includes the latencies from the DRAM to the logic layer
421 class HMC_2500_1x32(DDR3_1600_8x8
):
423 # two banks per device with each bank 4MB [2]
426 # 1x32 configuration, 1 device with 32 TSVs [2]
427 device_bus_width
= 32
429 # HMC is a BL8 device [2]
432 # Each device has a page (row buffer) size of 256 bytes [2]
433 device_rowbuffer_size
= '256B'
435 # 1x32 configuration, so 1 device [2]
438 # 4 layers so 4 ranks [2]
439 ranks_per_channel
= 4
441 # HMC has 2 banks per layer [2]
442 # Each layer represents a rank. With 4 layers and 8 banks in total, each
443 # layer has 2 banks; thus 2 banks per rank.
449 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
452 # Values using DRAMSpec HMC model [1]
458 # tRRD depends on the power supply network for each vendor.
459 # We assume a tRRD of a double bank approach to be equal to 4 clock
460 # cycles (Assumption)
463 # activation limit is set to 0 since there are only 2 banks per vault
467 # Values using DRAMSpec HMC model [1]
472 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
473 # 0.8 ns (Assumption)
476 # Value using DRAMSpec HMC model [1]
479 # The default page policy in the vault controllers is simple closed page
480 # [2] nevertheless 'close' policy opens and closes the row multiple times
481 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
482 page_policy
= 'close_adaptive'
484 # RoCoRaBaCh resembles the default address mapping in HMC
485 addr_mapping
= 'RoCoRaBaCh'
486 min_writes_per_switch
= 8
488 # These parameters do not directly correlate with buffer_size in real
489 # hardware. Nevertheless, their value has been tuned to achieve a
490 # bandwidth similar to the cycle-accurate model in [2]
491 write_buffer_size
= 32
492 read_buffer_size
= 32
494 # The static latency of the vault controllers is estimated to be smaller
495 # than a full DRAM channel controller
496 static_backend_latency
='4ns'
497 static_frontend_latency
='4ns'
499 # A single DDR3-2133 x64 channel refining a selected subset of the
500 # options for the DDR-1600 configuration, based on the same DDR3-1600
501 # 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
502 # consistent across the two configurations.
503 class DDR3_2133_8x8(DDR3_1600_8x8
):
507 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
518 # Current values from datasheet
530 # A single DDR4-2400 x64 channel (one command and address bus), with
531 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
532 # in an 16x4 configuration.
533 # Total channel capacity is 32GB
534 # 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
535 class DDR4_2400_16x4(DRAMCtrl
):
539 # 16x4 configuration, 16 devices each with a 4-bit interface
542 # DDR4 is a BL8 device
545 # Each device has a page (row buffer) size of 512 byte (1K columns x4)
546 device_rowbuffer_size
= '512B'
548 # 16x4 configuration, so 16 devices
549 devices_per_rank
= 16
551 # Match our DDR3 configurations which is dual rank
552 ranks_per_channel
= 2
554 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
555 # Set to 4 for x4 case
556 bank_groups_per_rank
= 4
558 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
559 # configurations). Currently we do not capture the additional
560 # constraints incurred by the bank groups
563 # override the default buffer sizes and go for something larger to
564 # accommodate the larger bank count
565 write_buffer_size
= 128
566 read_buffer_size
= 64
571 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
572 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
573 # With bank group architectures, tBURST represents the CAS-to-CAS
574 # delay for bursts to different bank groups (tCCD_S)
577 # @2400 data rate, tCCD_L is 6 CK
578 # CAS-to-CAS delay for bursts to the same bank group
579 # tBURST is equivalent to tCCD_S; no explicit parameter required
580 # for CAS-to-CAS delay for bursts to different bank groups
589 # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
592 # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
595 # tFAW for 512B page is MAX(16 CK, 13ns)
603 # Here using the average of WTR_S and WTR_L
606 # Greater of 4 CK or 7.5 ns
609 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
612 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
615 # <=85C, half for >85C
618 # active powerdown and precharge powerdown exit time
621 # self refresh exit time
622 # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
623 # tRFC + 10ns = 340ns
626 # Current values from datasheet
641 # A single DDR4-2400 x64 channel (one command and address bus), with
642 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
643 # in an 8x8 configuration.
644 # Total channel capacity is 16GB
645 # 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
646 class DDR4_2400_8x8(DDR4_2400_16x4
):
647 # 8x8 configuration, 8 devices each with an 8-bit interface
650 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
651 device_rowbuffer_size
= '1kB'
653 # 8x8 configuration, so 8 devices
656 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
661 # Current values from datasheet
668 # A single DDR4-2400 x64 channel (one command and address bus), with
669 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
670 # in an 4x16 configuration.
671 # Total channel capacity is 4GB
672 # 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
673 class DDR4_2400_4x16(DDR4_2400_16x4
):
674 # 4x16 configuration, 4 devices each with an 16-bit interface
675 device_bus_width
= 16
677 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
678 device_rowbuffer_size
= '2kB'
680 # 4x16 configuration, so 4 devices
683 # Single rank for x16
684 ranks_per_channel
= 1
686 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
687 # Set to 2 for x16 case
688 bank_groups_per_rank
= 2
690 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
691 # configurations). Currently we do not capture the additional
692 # constraints incurred by the bank groups
695 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
698 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
703 # Current values from datasheet
713 # A single LPDDR2-S4 x32 interface (one command/address bus), with
714 # default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
715 # in a 1x32 configuration.
716 class LPDDR2_S4_1066_1x32(DRAMCtrl
):
721 device_size
= '512MB'
723 # 1x32 configuration, 1 device with a 32-bit interface
724 device_bus_width
= 32
726 # LPDDR2_S4 is a BL4 and BL8 device
729 # Each device has a page (row buffer) size of 1KB
730 # (this depends on the memory density)
731 device_rowbuffer_size
= '1kB'
733 # 1x32 configuration, so 1 device
737 ranks_per_channel
= 1
739 # LPDDR2-S4 has 8 banks in all configurations
748 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
751 # Pre-charge one bank 15 ns (all banks 18 ns)
759 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
760 # Note this is a BL8 DDR device.
761 # Requests larger than 32 bytes are broken down into multiple requests
769 # active powerdown and precharge powerdown exit time
772 # self refresh exit time
775 # Irrespective of speed grade, tWTR is 7.5 ns
778 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
781 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
784 # Activate to activate irrespective of density and speed grade
787 # Irrespective of density, tFAW is 50 ns
791 # Current values from datasheet
813 # A single WideIO x128 interface (one command and address bus), with
814 # default timings based on an estimated WIO-200 8 Gbit part.
815 class WideIO_200_1x128(DRAMCtrl
):
820 device_size
= '1024MB'
822 # 1x128 configuration, 1 device with a 128-bit interface
823 device_bus_width
= 128
825 # This is a BL4 device
828 # Each device has a page (row buffer) size of 4KB
829 # (this depends on the memory density)
830 device_rowbuffer_size
= '4kB'
832 # 1x128 configuration, so 1 device
835 # Use one rank for a one-high die stack
836 ranks_per_channel
= 1
838 # WideIO has 4 banks in all configurations
850 # Read to precharge is same as the burst
853 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
854 # Note this is a BL4 SDR device.
860 # WIO 8 Gb, <=85C, half for >85C
863 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
866 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
869 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
872 # Activate to activate irrespective of density and speed grade
875 # Two instead of four activation window
879 # The WideIO specification does not provide current information
881 # A single LPDDR3 x32 interface (one command/address bus), with
882 # default timings based on a LPDDR3-1600 4 Gbit part (Micron
883 # EDF8132A1MC) in a 1x32 configuration.
884 class LPDDR3_1600_1x32(DRAMCtrl
):
889 device_size
= '512MB'
891 # 1x32 configuration, 1 device with a 32-bit interface
892 device_bus_width
= 32
894 # LPDDR3 is a BL8 device
897 # Each device has a page (row buffer) size of 4KB
898 device_rowbuffer_size
= '4kB'
900 # 1x32 configuration, so 1 device
903 # Technically the datasheet is a dual-rank package, but for
904 # comparison with the LPDDR2 config we stick to a single rank
905 ranks_per_channel
= 1
907 # LPDDR3 has 8 banks in all configurations
915 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
921 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
924 # Pre-charge one bank 18 ns (all banks 21 ns)
927 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
928 # Note this is a BL8 DDR device.
929 # Requests larger than 32 bytes are broken down into multiple requests
937 # active powerdown and precharge powerdown exit time
940 # self refresh exit time
943 # Irrespective of speed grade, tWTR is 7.5 ns
946 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
949 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
952 # Activate to activate irrespective of density and speed grade
955 # Irrespective of size, tFAW is 50 ns
959 # Current values from datasheet
981 # A single GDDR5 x64 interface, with
982 # default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
983 # H5GQ1H24AFR) in a 2x32 configuration.
984 class GDDR5_4000_2x32(DRAMCtrl
):
986 device_size
= '128MB'
988 # 2x32 configuration, 1 device with a 32-bit interface
989 device_bus_width
= 32
991 # GDDR5 is a BL8 device
994 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
995 device_rowbuffer_size
= '256B'
997 # 2x32 configuration, so 2 devices
1000 # assume single rank
1001 ranks_per_channel
= 1
1003 # GDDR5 has 4 bank groups
1004 bank_groups_per_rank
= 4
1006 # GDDR5 has 16 banks with 4 bank groups
1012 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
1013 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
1014 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
1015 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
1016 # With bank group architectures, tBURST represents the CAS-to-CAS
1017 # delay for bursts to different bank groups (tCCD_S)
1020 # @1000MHz data rate, tCCD_L is 3 CK
1021 # CAS-to-CAS delay for bursts to the same bank group
1022 # tBURST is equivalent to tCCD_S; no explicit parameter required
1023 # for CAS-to-CAS delay for bursts to different bank groups
1028 # tCL is not directly found in datasheet and assumed equal tRCD
1034 # RRD_S (different bank group)
1035 # RRD_S is 5.5 ns in datasheet.
1036 # rounded to the next multiple of tCK
1039 # RRD_L (same bank group)
1040 # RRD_L is 5.5 ns in datasheet.
1041 # rounded to the next multiple of tCK
1047 # Therefore, activation limit is set to 0
1048 activation_limit
= 0
1053 # Here using the average of WTR_S and WTR_L
1056 # Read-to-Precharge 2 CK
1062 # A single HBM x128 interface (one command and address bus), with
1063 # default timings based on data publically released
1064 # ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
1065 # IDD measurement values, and by extrapolating data from other classes.
1066 # Architecture values based on published HBM spec
1067 # A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
1068 class HBM_1000_4H_1x128(DRAMCtrl
):
1069 # HBM gen1 supports up to 8 128-bit physical channels
1070 # Configuration defines a single channel, with the capacity
1071 # set to (full_ stack_capacity / 8) based on 2Gb dies
1072 # To use all 8 channels, set 'channels' parameter to 8 in
1073 # system configuration
1075 # 128-bit interface legacy mode
1076 device_bus_width
= 128
1078 # HBM supports BL4 and BL2 (legacy mode only)
1081 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
1082 # with 8 channels, 128MB per channel
1083 device_size
= '128MB'
1085 device_rowbuffer_size
= '2kB'
1087 # 1x128 configuration
1088 devices_per_rank
= 1
1090 # HBM does not have a CS pin; set rank to 1
1091 ranks_per_channel
= 1
1093 # HBM has 8 or 16 banks depending on capacity
1094 # 2Gb dies have 8 banks
1097 # depending on frequency, bank groups may be required
1098 # will always have 4 bank groups when enabled
1099 # current specifications do not define the minimum frequency for
1100 # bank group architecture
1101 # setting bank_groups_per_rank to 0 to disable until range is defined
1102 bank_groups_per_rank
= 0
1104 # 500 MHz for 1Gbps DDR data rate
1107 # use values from IDD measurement in JEDEC spec
1108 # use tRP value for tRCD and tCL similar to other classes
1114 # BL2 and BL4 supported, default to BL4
1115 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
1118 # value for 2Gb device from JEDEC spec
1121 # value for 2Gb device from JEDEC spec
1124 # extrapolate the following from LPDDR configs, using ns values
1125 # to minimize burst length, prefetch differences
1130 # start with 2 cycles turnaround, similar to other memory classes
1131 # could be more with variations across the stack
1134 # single rank device, set to 0
1137 # from MemCon example, tRRD is 4ns with 2ns tCK
1140 # from MemCon example, tFAW is 30ns with 2ns tCK
1142 activation_limit
= 4
1147 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1150 # A single HBM x64 interface (one command and address bus), with
1151 # default timings based on HBM gen1 and data publically released
1152 # A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1153 # Note: This defines a pseudo-channel with a unique controller
1154 # instantiated per pseudo-channel
1155 # Stay at same IO rate (1Gbps) to maintain timing relationship with
1156 # HBM gen1 class (HBM_1000_4H_x128) where possible
1157 class HBM_1000_4H_1x64(HBM_1000_4H_1x128
):
1158 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1159 # Configuration defines a single pseudo channel, with the capacity
1160 # set to (full_ stack_capacity / 16) based on 8Gb dies
1161 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1162 # system configuration
1164 # 64-bit pseudo-channle interface
1165 device_bus_width
= 64
1167 # HBM pseudo-channel only supports BL4
1170 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1171 # with 16 channels, 256MB per channel
1172 device_size
= '256MB'
1174 # page size is halved with pseudo-channel; maintaining the same same number
1175 # of rows per pseudo-channel with 2X banks across 2 channels
1176 device_rowbuffer_size
= '1kB'
1178 # HBM has 8 or 16 banks depending on capacity
1179 # Starting with 4Gb dies, 16 banks are defined
1182 # reset tRFC for larger, 8Gb device
1183 # use HBM1 4Gb value as a starting point
1186 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1188 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1192 # active powerdown and precharge powerdown exit time
1195 # self refresh exit time