1 # Copyright (c) 2012-2018 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2013 Amin Farmahini-Farahani
14 # Copyright (c) 2015 University of Kaiserslautern
15 # Copyright (c) 2015 The University of Bologna
16 # All rights reserved.
18 # Redistribution and use in source and binary forms, with or without
19 # modification, are permitted provided that the following conditions are
20 # met: redistributions of source code must retain the above copyright
21 # notice, this list of conditions and the following disclaimer;
22 # redistributions in binary form must reproduce the above copyright
23 # notice, this list of conditions and the following disclaimer in the
24 # documentation and/or other materials provided with the distribution;
25 # neither the name of the copyright holders nor the names of its
26 # contributors may be used to endorse or promote products derived from
27 # this software without specific prior written permission.
29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 # Authors: Andreas Hansson
47 from m5
.params
import *
48 from m5
.proxy
import *
49 from AbstractMemory
import *
50 from QoSMemCtrl
import *
52 # Enum for memory scheduling algorithms, currently First-Come
53 # First-Served and a First-Row Hit then First-Come First-Served
54 class MemSched(Enum
): vals
= ['fcfs', 'frfcfs']
56 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
57 # channel, rank, bank, row and column, respectively, and going from
58 # MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
59 # suitable for an open-page policy, optimising for sequential accesses
60 # hitting in the open row. For a closed-page policy, RoCoRaBaCh
61 # maximises parallelism.
62 class AddrMap(Enum
): vals
= ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
64 # Enum for the page policy, either open, open_adaptive, close, or
66 class PageManage(Enum
): vals
= ['open', 'open_adaptive', 'close',
69 # DRAMCtrl is a single-channel single-ported DRAM controller model
70 # that aims to model the most important system-level performance
71 # effects of a DRAM without getting into too much detail of the DRAM
73 class DRAMCtrl(QoSMemCtrl
):
75 cxx_header
= "mem/dram_ctrl.hh"
77 # single-ported on the system interface side, instantiate with a
78 # bus in front of the controller for multiple ports
79 port
= SlavePort("Slave port")
81 # the basic configuration of the controller architecture, note
82 # that each entry corresponds to a burst for the specific DRAM
83 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
84 # the cacheline size or request/packet size
85 write_buffer_size
= Param
.Unsigned(64, "Number of write queue entries")
86 read_buffer_size
= Param
.Unsigned(32, "Number of read queue entries")
88 # threshold in percent for when to forcefully trigger writes and
89 # start emptying the write buffer
90 write_high_thresh_perc
= Param
.Percent(85, "Threshold to force writes")
92 # threshold in percentage for when to start writes if the read
94 write_low_thresh_perc
= Param
.Percent(50, "Threshold to start writes")
96 # minimum write bursts to schedule before switching back to reads
97 min_writes_per_switch
= Param
.Unsigned(16, "Minimum write bursts before "
100 # scheduler, address map and page policy
101 mem_sched_policy
= Param
.MemSched('frfcfs', "Memory scheduling policy")
102 addr_mapping
= Param
.AddrMap('RoRaBaCoCh', "Address mapping policy")
103 page_policy
= Param
.PageManage('open_adaptive', "Page management policy")
105 # enforce a limit on the number of accesses per row
106 max_accesses_per_row
= Param
.Unsigned(16, "Max accesses per row before "
109 # size of DRAM Chip in Bytes
110 device_size
= Param
.MemorySize("Size of DRAM chip")
112 # pipeline latency of the controller and PHY, split into a
113 # frontend part and a backend part, with reads and writes serviced
114 # by the queues only seeing the frontend contribution, and reads
115 # serviced by the memory seeing the sum of the two
116 static_frontend_latency
= Param
.Latency("10ns", "Static frontend latency")
117 static_backend_latency
= Param
.Latency("10ns", "Static backend latency")
119 # the physical organisation of the DRAM
120 device_bus_width
= Param
.Unsigned("data bus width in bits for each DRAM "\
122 burst_length
= Param
.Unsigned("Burst lenght (BL) in beats")
123 device_rowbuffer_size
= Param
.MemorySize("Page (row buffer) size per "\
125 devices_per_rank
= Param
.Unsigned("Number of devices/chips per rank")
126 ranks_per_channel
= Param
.Unsigned("Number of ranks per channel")
128 # default to 0 bank groups per rank, indicating bank group architecture
130 # update per memory class when bank group architecture is supported
131 bank_groups_per_rank
= Param
.Unsigned(0, "Number of bank groups per rank")
132 banks_per_rank
= Param
.Unsigned("Number of banks per rank")
133 # only used for the address mapping as the controller by
134 # construction is a single channel and multiple controllers have
135 # to be instantiated for a multi-channel configuration
136 channels
= Param
.Unsigned(1, "Number of channels")
138 # For power modelling we need to know if the DRAM has a DLL or not
139 dll
= Param
.Bool(True, "DRAM has DLL or not")
141 # DRAMPower provides in addition to the core power, the possibility to
142 # include RD/WR termination and IO power. This calculation assumes some
143 # default values. The integration of DRAMPower with gem5 does not include
144 # IO and RD/WR termination power by default. This might be added as an
145 # additional feature in the future.
147 # timing behaviour and constraints - all in nanoseconds
149 # the base clock period of the DRAM
150 tCK
= Param
.Latency("Clock period")
152 # the amount of time in nanoseconds from issuing an activate command
153 # to the data being available in the row buffer for a read/write
154 tRCD
= Param
.Latency("RAS to CAS delay")
156 # the time from issuing a read/write command to seeing the actual data
157 tCL
= Param
.Latency("CAS latency")
159 # minimum time between a precharge and subsequent activate
160 tRP
= Param
.Latency("Row precharge time")
162 # minimum time between an activate and a precharge to the same row
163 tRAS
= Param
.Latency("ACT to PRE delay")
165 # minimum time between a write data transfer and a precharge
166 tWR
= Param
.Latency("Write recovery time")
168 # minimum time between a read and precharge command
169 tRTP
= Param
.Latency("Read to precharge")
171 # time to complete a burst transfer, typically the burst length
172 # divided by two due to the DDR bus, but by making it a parameter
173 # it is easier to also evaluate SDR memories like WideIO.
174 # This parameter has to account for burst length.
175 # Read/Write requests with data size larger than one full burst are broken
176 # down into multiple requests in the controller
177 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
178 # With bank group architectures, tBURST represents the CAS-to-CAS
179 # delay for bursts to different bank groups (tCCD_S)
180 tBURST
= Param
.Latency("Burst duration (for DDR burst length / 2 cycles)")
182 # CAS-to-CAS delay for bursts to the same bank group
183 # only utilized with bank group architectures; set to 0 for default case
184 # tBURST is equivalent to tCCD_S; no explicit parameter required
185 # for CAS-to-CAS delay for bursts to different bank groups
186 tCCD_L
= Param
.Latency("0ns", "Same bank group CAS to CAS delay")
188 # Write-to-Write delay for bursts to the same bank group
189 # only utilized with bank group architectures; set to 0 for default case
190 # This will be used to enable different same bank group delays
191 # for writes versus reads
192 tCCD_L_WR
= Param
.Latency(Self
.tCCD_L
,
193 "Same bank group Write to Write delay")
195 # time taken to complete one refresh cycle (N rows in all banks)
196 tRFC
= Param
.Latency("Refresh cycle time")
198 # refresh command interval, how often a "ref" command needs
199 # to be sent. It is 7.8 us for a 64ms refresh requirement
200 tREFI
= Param
.Latency("Refresh command interval")
202 # write-to-read, same rank turnaround penalty
203 tWTR
= Param
.Latency("Write to read, same rank switching time")
205 # read-to-write, same rank turnaround penalty
206 tRTW
= Param
.Latency("Read to write, same rank switching time")
208 # rank-to-rank bus delay penalty
209 # this does not correlate to a memory timing parameter and encompasses:
210 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
211 # different rank bus delay
212 tCS
= Param
.Latency("Rank to rank switching time")
214 # minimum row activate to row activate delay time
215 tRRD
= Param
.Latency("ACT to ACT delay")
217 # only utilized with bank group architectures; set to 0 for default case
218 tRRD_L
= Param
.Latency("0ns", "Same bank group ACT to ACT delay")
220 # time window in which a maximum number of activates are allowed
221 # to take place, set to 0 to disable
222 tXAW
= Param
.Latency("X activation window")
223 activation_limit
= Param
.Unsigned("Max number of activates in window")
225 # time to exit power-down mode
226 # Exit power-down to next valid command delay
227 tXP
= Param
.Latency("0ns", "Power-up Delay")
229 # Exit Powerdown to commands requiring a locked DLL
230 tXPDLL
= Param
.Latency("0ns", "Power-up Delay with locked DLL")
232 # time to exit self-refresh mode
233 tXS
= Param
.Latency("0ns", "Self-refresh exit latency")
235 # time to exit self-refresh mode with locked DLL
236 tXSDLL
= Param
.Latency("0ns", "Self-refresh exit latency DLL")
238 # Currently rolled into other params
239 ######################################################################
241 # tRC - assumed to be tRAS + tRP
243 # Power Behaviour and Constraints
244 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
245 # defined as VDD and VDD2. Each current is defined for each voltage domain
246 # separately. For example, current IDD0 is active-precharge current for
247 # voltage domain VDD and current IDD02 is active-precharge current for
248 # voltage domain VDD2.
249 # By default all currents are set to 0mA. Users who are only interested in
250 # the performance of DRAMs can leave them at 0.
252 # Operating 1 Bank Active-Precharge current
253 IDD0
= Param
.Current("0mA", "Active precharge current")
255 # Operating 1 Bank Active-Precharge current multiple voltage Range
256 IDD02
= Param
.Current("0mA", "Active precharge current VDD2")
258 # Precharge Power-down Current: Slow exit
259 IDD2P0
= Param
.Current("0mA", "Precharge Powerdown slow")
261 # Precharge Power-down Current: Slow exit multiple voltage Range
262 IDD2P02
= Param
.Current("0mA", "Precharge Powerdown slow VDD2")
264 # Precharge Power-down Current: Fast exit
265 IDD2P1
= Param
.Current("0mA", "Precharge Powerdown fast")
267 # Precharge Power-down Current: Fast exit multiple voltage Range
268 IDD2P12
= Param
.Current("0mA", "Precharge Powerdown fast VDD2")
270 # Precharge Standby current
271 IDD2N
= Param
.Current("0mA", "Precharge Standby current")
273 # Precharge Standby current multiple voltage range
274 IDD2N2
= Param
.Current("0mA", "Precharge Standby current VDD2")
276 # Active Power-down current: slow exit
277 IDD3P0
= Param
.Current("0mA", "Active Powerdown slow")
279 # Active Power-down current: slow exit multiple voltage range
280 IDD3P02
= Param
.Current("0mA", "Active Powerdown slow VDD2")
282 # Active Power-down current : fast exit
283 IDD3P1
= Param
.Current("0mA", "Active Powerdown fast")
285 # Active Power-down current : fast exit multiple voltage range
286 IDD3P12
= Param
.Current("0mA", "Active Powerdown fast VDD2")
288 # Active Standby current
289 IDD3N
= Param
.Current("0mA", "Active Standby current")
291 # Active Standby current multiple voltage range
292 IDD3N2
= Param
.Current("0mA", "Active Standby current VDD2")
294 # Burst Read Operating Current
295 IDD4R
= Param
.Current("0mA", "READ current")
297 # Burst Read Operating Current multiple voltage range
298 IDD4R2
= Param
.Current("0mA", "READ current VDD2")
300 # Burst Write Operating Current
301 IDD4W
= Param
.Current("0mA", "WRITE current")
303 # Burst Write Operating Current multiple voltage range
304 IDD4W2
= Param
.Current("0mA", "WRITE current VDD2")
307 IDD5
= Param
.Current("0mA", "Refresh current")
309 # Refresh Current multiple voltage range
310 IDD52
= Param
.Current("0mA", "Refresh current VDD2")
312 # Self-Refresh Current
313 IDD6
= Param
.Current("0mA", "Self-refresh Current")
315 # Self-Refresh Current multiple voltage range
316 IDD62
= Param
.Current("0mA", "Self-refresh Current VDD2")
318 # Main voltage range of the DRAM
319 VDD
= Param
.Voltage("0V", "Main Voltage Range")
321 # Second voltage range defined by some DRAMs
322 VDD2
= Param
.Voltage("0V", "2nd Voltage Range")
324 # A single DDR3-1600 x64 channel (one command and address bus), with
325 # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
326 # an 8x8 configuration.
327 class DDR3_1600_8x8(DRAMCtrl
):
328 # size of device in bytes
329 device_size
= '512MB'
331 # 8x8 configuration, 8 devices each with an 8-bit interface
334 # DDR3 is a BL8 device
337 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
338 device_rowbuffer_size
= '1kB'
340 # 8x8 configuration, so 8 devices
344 ranks_per_channel
= 2
346 # DDR3 has 8 banks in all configurations
352 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
367 # Greater of 4 CK or 7.5 ns
370 # Greater of 4 CK or 7.5 ns
373 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
376 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
379 # <=85C, half for >85C
382 # active powerdown and precharge powerdown exit time
385 # self refresh exit time
388 # Current values from datasheet Die Rev E,J
400 # A single HMC-2500 x32 model based on:
401 # [1] DRAMSpec: a high-level DRAM bank modelling tool
402 # developed at the University of Kaiserslautern. This high level tool
403 # uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
404 # estimate the DRAM bank latency and power numbers.
405 # [2] High performance AXI-4.0 based interconnect for extensible smart memory
406 # cubes (E. Azarkhish et. al)
407 # Assumed for the HMC model is a 30 nm technology node.
408 # The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
410 # Each layer has 16 vaults and each vault consists of 2 banks per layer.
411 # In order to be able to use the same controller used for 2D DRAM generations
412 # for HMC, the following analogy is done:
413 # Channel (DDR) => Vault (HMC)
414 # device_size (DDR) => size of a single layer in a vault
415 # ranks per channel (DDR) => number of layers
416 # banks per rank (DDR) => banks per layer
417 # devices per rank (DDR) => devices per layer ( 1 for HMC).
418 # The parameters for which no input is available are inherited from the DDR3
420 # This configuration includes the latencies from the DRAM to the logic layer
422 class HMC_2500_1x32(DDR3_1600_8x8
):
424 # two banks per device with each bank 4MB [2]
427 # 1x32 configuration, 1 device with 32 TSVs [2]
428 device_bus_width
= 32
430 # HMC is a BL8 device [2]
433 # Each device has a page (row buffer) size of 256 bytes [2]
434 device_rowbuffer_size
= '256B'
436 # 1x32 configuration, so 1 device [2]
439 # 4 layers so 4 ranks [2]
440 ranks_per_channel
= 4
442 # HMC has 2 banks per layer [2]
443 # Each layer represents a rank. With 4 layers and 8 banks in total, each
444 # layer has 2 banks; thus 2 banks per rank.
450 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
453 # Values using DRAMSpec HMC model [1]
459 # tRRD depends on the power supply network for each vendor.
460 # We assume a tRRD of a double bank approach to be equal to 4 clock
461 # cycles (Assumption)
464 # activation limit is set to 0 since there are only 2 banks per vault
468 # Values using DRAMSpec HMC model [1]
473 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
474 # 0.8 ns (Assumption)
477 # Value using DRAMSpec HMC model [1]
480 # The default page policy in the vault controllers is simple closed page
481 # [2] nevertheless 'close' policy opens and closes the row multiple times
482 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
483 page_policy
= 'close_adaptive'
485 # RoCoRaBaCh resembles the default address mapping in HMC
486 addr_mapping
= 'RoCoRaBaCh'
487 min_writes_per_switch
= 8
489 # These parameters do not directly correlate with buffer_size in real
490 # hardware. Nevertheless, their value has been tuned to achieve a
491 # bandwidth similar to the cycle-accurate model in [2]
492 write_buffer_size
= 32
493 read_buffer_size
= 32
495 # The static latency of the vault controllers is estimated to be smaller
496 # than a full DRAM channel controller
497 static_backend_latency
='4ns'
498 static_frontend_latency
='4ns'
500 # A single DDR3-2133 x64 channel refining a selected subset of the
501 # options for the DDR-1600 configuration, based on the same DDR3-1600
502 # 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
503 # consistent across the two configurations.
504 class DDR3_2133_8x8(DDR3_1600_8x8
):
508 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
519 # Current values from datasheet
531 # A single DDR4-2400 x64 channel (one command and address bus), with
532 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
533 # in an 16x4 configuration.
534 # Total channel capacity is 32GB
535 # 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
536 class DDR4_2400_16x4(DRAMCtrl
):
540 # 16x4 configuration, 16 devices each with a 4-bit interface
543 # DDR4 is a BL8 device
546 # Each device has a page (row buffer) size of 512 byte (1K columns x4)
547 device_rowbuffer_size
= '512B'
549 # 16x4 configuration, so 16 devices
550 devices_per_rank
= 16
552 # Match our DDR3 configurations which is dual rank
553 ranks_per_channel
= 2
555 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
556 # Set to 4 for x4 case
557 bank_groups_per_rank
= 4
559 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
560 # configurations). Currently we do not capture the additional
561 # constraints incurred by the bank groups
564 # override the default buffer sizes and go for something larger to
565 # accommodate the larger bank count
566 write_buffer_size
= 128
567 read_buffer_size
= 64
572 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
573 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
574 # With bank group architectures, tBURST represents the CAS-to-CAS
575 # delay for bursts to different bank groups (tCCD_S)
578 # @2400 data rate, tCCD_L is 6 CK
579 # CAS-to-CAS delay for bursts to the same bank group
580 # tBURST is equivalent to tCCD_S; no explicit parameter required
581 # for CAS-to-CAS delay for bursts to different bank groups
590 # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
593 # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
596 # tFAW for 512B page is MAX(16 CK, 13ns)
604 # Here using the average of WTR_S and WTR_L
607 # Greater of 4 CK or 7.5 ns
610 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
613 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
616 # <=85C, half for >85C
619 # active powerdown and precharge powerdown exit time
622 # self refresh exit time
623 # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
624 # tRFC + 10ns = 340ns
627 # Current values from datasheet
642 # A single DDR4-2400 x64 channel (one command and address bus), with
643 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
644 # in an 8x8 configuration.
645 # Total channel capacity is 16GB
646 # 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
647 class DDR4_2400_8x8(DDR4_2400_16x4
):
648 # 8x8 configuration, 8 devices each with an 8-bit interface
651 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
652 device_rowbuffer_size
= '1kB'
654 # 8x8 configuration, so 8 devices
657 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
662 # Current values from datasheet
669 # A single DDR4-2400 x64 channel (one command and address bus), with
670 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
671 # in an 4x16 configuration.
672 # Total channel capacity is 4GB
673 # 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
674 class DDR4_2400_4x16(DDR4_2400_16x4
):
675 # 4x16 configuration, 4 devices each with an 16-bit interface
676 device_bus_width
= 16
678 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
679 device_rowbuffer_size
= '2kB'
681 # 4x16 configuration, so 4 devices
684 # Single rank for x16
685 ranks_per_channel
= 1
687 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
688 # Set to 2 for x16 case
689 bank_groups_per_rank
= 2
691 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
692 # configurations). Currently we do not capture the additional
693 # constraints incurred by the bank groups
696 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
699 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
704 # Current values from datasheet
714 # A single LPDDR2-S4 x32 interface (one command/address bus), with
715 # default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
716 # in a 1x32 configuration.
717 class LPDDR2_S4_1066_1x32(DRAMCtrl
):
722 device_size
= '512MB'
724 # 1x32 configuration, 1 device with a 32-bit interface
725 device_bus_width
= 32
727 # LPDDR2_S4 is a BL4 and BL8 device
730 # Each device has a page (row buffer) size of 1KB
731 # (this depends on the memory density)
732 device_rowbuffer_size
= '1kB'
734 # 1x32 configuration, so 1 device
738 ranks_per_channel
= 1
740 # LPDDR2-S4 has 8 banks in all configurations
749 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
752 # Pre-charge one bank 15 ns (all banks 18 ns)
760 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
761 # Note this is a BL8 DDR device.
762 # Requests larger than 32 bytes are broken down into multiple requests
770 # active powerdown and precharge powerdown exit time
773 # self refresh exit time
776 # Irrespective of speed grade, tWTR is 7.5 ns
779 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
782 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
785 # Activate to activate irrespective of density and speed grade
788 # Irrespective of density, tFAW is 50 ns
792 # Current values from datasheet
814 # A single WideIO x128 interface (one command and address bus), with
815 # default timings based on an estimated WIO-200 8 Gbit part.
816 class WideIO_200_1x128(DRAMCtrl
):
821 device_size
= '1024MB'
823 # 1x128 configuration, 1 device with a 128-bit interface
824 device_bus_width
= 128
826 # This is a BL4 device
829 # Each device has a page (row buffer) size of 4KB
830 # (this depends on the memory density)
831 device_rowbuffer_size
= '4kB'
833 # 1x128 configuration, so 1 device
836 # Use one rank for a one-high die stack
837 ranks_per_channel
= 1
839 # WideIO has 4 banks in all configurations
851 # Read to precharge is same as the burst
854 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
855 # Note this is a BL4 SDR device.
861 # WIO 8 Gb, <=85C, half for >85C
864 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
867 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
870 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
873 # Activate to activate irrespective of density and speed grade
876 # Two instead of four activation window
880 # The WideIO specification does not provide current information
882 # A single LPDDR3 x32 interface (one command/address bus), with
883 # default timings based on a LPDDR3-1600 4 Gbit part (Micron
884 # EDF8132A1MC) in a 1x32 configuration.
885 class LPDDR3_1600_1x32(DRAMCtrl
):
890 device_size
= '512MB'
892 # 1x32 configuration, 1 device with a 32-bit interface
893 device_bus_width
= 32
895 # LPDDR3 is a BL8 device
898 # Each device has a page (row buffer) size of 4KB
899 device_rowbuffer_size
= '4kB'
901 # 1x32 configuration, so 1 device
904 # Technically the datasheet is a dual-rank package, but for
905 # comparison with the LPDDR2 config we stick to a single rank
906 ranks_per_channel
= 1
908 # LPDDR3 has 8 banks in all configurations
916 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
922 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
925 # Pre-charge one bank 18 ns (all banks 21 ns)
928 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
929 # Note this is a BL8 DDR device.
930 # Requests larger than 32 bytes are broken down into multiple requests
938 # active powerdown and precharge powerdown exit time
941 # self refresh exit time
944 # Irrespective of speed grade, tWTR is 7.5 ns
947 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
950 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
953 # Activate to activate irrespective of density and speed grade
956 # Irrespective of size, tFAW is 50 ns
960 # Current values from datasheet
982 # A single GDDR5 x64 interface, with
983 # default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
984 # H5GQ1H24AFR) in a 2x32 configuration.
985 class GDDR5_4000_2x32(DRAMCtrl
):
987 device_size
= '128MB'
989 # 2x32 configuration, 1 device with a 32-bit interface
990 device_bus_width
= 32
992 # GDDR5 is a BL8 device
995 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
996 device_rowbuffer_size
= '256B'
998 # 2x32 configuration, so 2 devices
1001 # assume single rank
1002 ranks_per_channel
= 1
1004 # GDDR5 has 4 bank groups
1005 bank_groups_per_rank
= 4
1007 # GDDR5 has 16 banks with 4 bank groups
1013 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
1014 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
1015 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
1016 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
1017 # With bank group architectures, tBURST represents the CAS-to-CAS
1018 # delay for bursts to different bank groups (tCCD_S)
1021 # @1000MHz data rate, tCCD_L is 3 CK
1022 # CAS-to-CAS delay for bursts to the same bank group
1023 # tBURST is equivalent to tCCD_S; no explicit parameter required
1024 # for CAS-to-CAS delay for bursts to different bank groups
1029 # tCL is not directly found in datasheet and assumed equal tRCD
1035 # RRD_S (different bank group)
1036 # RRD_S is 5.5 ns in datasheet.
1037 # rounded to the next multiple of tCK
1040 # RRD_L (same bank group)
1041 # RRD_L is 5.5 ns in datasheet.
1042 # rounded to the next multiple of tCK
1048 # Therefore, activation limit is set to 0
1049 activation_limit
= 0
1054 # Here using the average of WTR_S and WTR_L
1057 # Read-to-Precharge 2 CK
1063 # A single HBM x128 interface (one command and address bus), with
1064 # default timings based on data publically released
1065 # ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
1066 # IDD measurement values, and by extrapolating data from other classes.
1067 # Architecture values based on published HBM spec
1068 # A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
1069 class HBM_1000_4H_1x128(DRAMCtrl
):
1070 # HBM gen1 supports up to 8 128-bit physical channels
1071 # Configuration defines a single channel, with the capacity
1072 # set to (full_ stack_capacity / 8) based on 2Gb dies
1073 # To use all 8 channels, set 'channels' parameter to 8 in
1074 # system configuration
1076 # 128-bit interface legacy mode
1077 device_bus_width
= 128
1079 # HBM supports BL4 and BL2 (legacy mode only)
1082 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
1083 # with 8 channels, 128MB per channel
1084 device_size
= '128MB'
1086 device_rowbuffer_size
= '2kB'
1088 # 1x128 configuration
1089 devices_per_rank
= 1
1091 # HBM does not have a CS pin; set rank to 1
1092 ranks_per_channel
= 1
1094 # HBM has 8 or 16 banks depending on capacity
1095 # 2Gb dies have 8 banks
1098 # depending on frequency, bank groups may be required
1099 # will always have 4 bank groups when enabled
1100 # current specifications do not define the minimum frequency for
1101 # bank group architecture
1102 # setting bank_groups_per_rank to 0 to disable until range is defined
1103 bank_groups_per_rank
= 0
1105 # 500 MHz for 1Gbps DDR data rate
1108 # use values from IDD measurement in JEDEC spec
1109 # use tRP value for tRCD and tCL similar to other classes
1115 # BL2 and BL4 supported, default to BL4
1116 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
1119 # value for 2Gb device from JEDEC spec
1122 # value for 2Gb device from JEDEC spec
1125 # extrapolate the following from LPDDR configs, using ns values
1126 # to minimize burst length, prefetch differences
1131 # start with 2 cycles turnaround, similar to other memory classes
1132 # could be more with variations across the stack
1135 # single rank device, set to 0
1138 # from MemCon example, tRRD is 4ns with 2ns tCK
1141 # from MemCon example, tFAW is 30ns with 2ns tCK
1143 activation_limit
= 4
1148 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1151 # A single HBM x64 interface (one command and address bus), with
1152 # default timings based on HBM gen1 and data publically released
1153 # A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1154 # Note: This defines a pseudo-channel with a unique controller
1155 # instantiated per pseudo-channel
1156 # Stay at same IO rate (1Gbps) to maintain timing relationship with
1157 # HBM gen1 class (HBM_1000_4H_x128) where possible
1158 class HBM_1000_4H_1x64(HBM_1000_4H_1x128
):
1159 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1160 # Configuration defines a single pseudo channel, with the capacity
1161 # set to (full_ stack_capacity / 16) based on 8Gb dies
1162 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1163 # system configuration
1165 # 64-bit pseudo-channle interface
1166 device_bus_width
= 64
1168 # HBM pseudo-channel only supports BL4
1171 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1172 # with 16 channels, 256MB per channel
1173 device_size
= '256MB'
1175 # page size is halved with pseudo-channel; maintaining the same same number
1176 # of rows per pseudo-channel with 2X banks across 2 channels
1177 device_rowbuffer_size
= '1kB'
1179 # HBM has 8 or 16 banks depending on capacity
1180 # Starting with 4Gb dies, 16 banks are defined
1183 # reset tRFC for larger, 8Gb device
1184 # use HBM1 4Gb value as a starting point
1187 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1189 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1193 # active powerdown and precharge powerdown exit time
1196 # self refresh exit time