1 # Copyright (c) 2012-2014 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2013 Amin Farmahini-Farahani
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
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23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 # Authors: Andreas Hansson
42 from m5
.params
import *
43 from AbstractMemory
import *
45 # Enum for memory scheduling algorithms, currently First-Come
46 # First-Served and a First-Row Hit then First-Come First-Served
47 class MemSched(Enum
): vals
= ['fcfs', 'frfcfs']
49 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
50 # channel, rank, bank, row and column, respectively, and going from
51 # MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
52 # suitable for an open-page policy, optimising for sequential accesses
53 # hitting in the open row. For a closed-page policy, RoCoRaBaCh
54 # maximises parallelism.
55 class AddrMap(Enum
): vals
= ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
57 # Enum for the page policy, either open, open_adaptive, close, or
59 class PageManage(Enum
): vals
= ['open', 'open_adaptive', 'close',
62 # DRAMCtrl is a single-channel single-ported DRAM controller model
63 # that aims to model the most important system-level performance
64 # effects of a DRAM without getting into too much detail of the DRAM
66 class DRAMCtrl(AbstractMemory
):
68 cxx_header
= "mem/dram_ctrl.hh"
70 # single-ported on the system interface side, instantiate with a
71 # bus in front of the controller for multiple ports
72 port
= SlavePort("Slave port")
74 # the basic configuration of the controller architecture
75 write_buffer_size
= Param
.Unsigned(64, "Number of write queue entries")
76 read_buffer_size
= Param
.Unsigned(32, "Number of read queue entries")
78 # threshold in percent for when to forcefully trigger writes and
79 # start emptying the write buffer
80 write_high_thresh_perc
= Param
.Percent(85, "Threshold to force writes")
82 # threshold in percentage for when to start writes if the read
84 write_low_thresh_perc
= Param
.Percent(50, "Threshold to start writes")
86 # minimum write bursts to schedule before switching back to reads
87 min_writes_per_switch
= Param
.Unsigned(16, "Minimum write bursts before "
90 # scheduler, address map and page policy
91 mem_sched_policy
= Param
.MemSched('frfcfs', "Memory scheduling policy")
92 addr_mapping
= Param
.AddrMap('RoRaBaChCo', "Address mapping policy")
93 page_policy
= Param
.PageManage('open_adaptive', "Page management policy")
95 # enforce a limit on the number of accesses per row
96 max_accesses_per_row
= Param
.Unsigned(16, "Max accesses per row before "
99 # pipeline latency of the controller and PHY, split into a
100 # frontend part and a backend part, with reads and writes serviced
101 # by the queues only seeing the frontend contribution, and reads
102 # serviced by the memory seeing the sum of the two
103 static_frontend_latency
= Param
.Latency("10ns", "Static frontend latency")
104 static_backend_latency
= Param
.Latency("10ns", "Static backend latency")
106 # the physical organisation of the DRAM
107 device_bus_width
= Param
.Unsigned("data bus width in bits for each DRAM "\
109 burst_length
= Param
.Unsigned("Burst lenght (BL) in beats")
110 device_rowbuffer_size
= Param
.MemorySize("Page (row buffer) size per "\
112 devices_per_rank
= Param
.Unsigned("Number of devices/chips per rank")
113 ranks_per_channel
= Param
.Unsigned("Number of ranks per channel")
115 # default to 0 bank groups per rank, indicating bank group architecture
117 # update per memory class when bank group architecture is supported
118 bank_groups_per_rank
= Param
.Unsigned(0, "Number of bank groups per rank")
119 banks_per_rank
= Param
.Unsigned("Number of banks per rank")
120 # only used for the address mapping as the controller by
121 # construction is a single channel and multiple controllers have
122 # to be instantiated for a multi-channel configuration
123 channels
= Param
.Unsigned(1, "Number of channels")
125 # For power modelling we need to know if the DRAM has a DLL or not
126 dll
= Param
.Bool(True, "DRAM has DLL or not")
128 # DRAMPower provides in addition to the core power, the possibility to
129 # include RD/WR termination and IO power. This calculation assumes some
130 # default values. The integration of DRAMPower with gem5 does not include
131 # IO and RD/WR termination power by default. This might be added as an
132 # additional feature in the future.
134 # timing behaviour and constraints - all in nanoseconds
136 # the base clock period of the DRAM
137 tCK
= Param
.Latency("Clock period")
139 # the amount of time in nanoseconds from issuing an activate command
140 # to the data being available in the row buffer for a read/write
141 tRCD
= Param
.Latency("RAS to CAS delay")
143 # the time from issuing a read/write command to seeing the actual data
144 tCL
= Param
.Latency("CAS latency")
146 # minimum time between a precharge and subsequent activate
147 tRP
= Param
.Latency("Row precharge time")
149 # minimum time between an activate and a precharge to the same row
150 tRAS
= Param
.Latency("ACT to PRE delay")
152 # minimum time between a write data transfer and a precharge
153 tWR
= Param
.Latency("Write recovery time")
155 # minimum time between a read and precharge command
156 tRTP
= Param
.Latency("Read to precharge")
158 # time to complete a burst transfer, typically the burst length
159 # divided by two due to the DDR bus, but by making it a parameter
160 # it is easier to also evaluate SDR memories like WideIO.
161 # This parameter has to account for burst length.
162 # Read/Write requests with data size larger than one full burst are broken
163 # down into multiple requests in the controller
164 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
165 # With bank group architectures, tBURST represents the CAS-to-CAS
166 # delay for bursts to different bank groups (tCCD_S)
167 tBURST
= Param
.Latency("Burst duration (for DDR burst length / 2 cycles)")
169 # CAS-to-CAS delay for bursts to the same bank group
170 # only utilized with bank group architectures; set to 0 for default case
171 # tBURST is equivalent to tCCD_S; no explicit parameter required
172 # for CAS-to-CAS delay for bursts to different bank groups
173 tCCD_L
= Param
.Latency("0ns", "Same bank group CAS to CAS delay")
175 # time taken to complete one refresh cycle (N rows in all banks)
176 tRFC
= Param
.Latency("Refresh cycle time")
178 # refresh command interval, how often a "ref" command needs
179 # to be sent. It is 7.8 us for a 64ms refresh requirement
180 tREFI
= Param
.Latency("Refresh command interval")
182 # write-to-read, same rank turnaround penalty
183 tWTR
= Param
.Latency("Write to read, same rank switching time")
185 # read-to-write, same rank turnaround penalty
186 tRTW
= Param
.Latency("Read to write, same rank switching time")
188 # rank-to-rank bus delay penalty
189 # this does not correlate to a memory timing parameter and encompasses:
190 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
191 # different rank bus delay
192 tCS
= Param
.Latency("Rank to rank switching time")
194 # minimum row activate to row activate delay time
195 tRRD
= Param
.Latency("ACT to ACT delay")
197 # only utilized with bank group architectures; set to 0 for default case
198 tRRD_L
= Param
.Latency("0ns", "Same bank group ACT to ACT delay")
200 # time window in which a maximum number of activates are allowed
201 # to take place, set to 0 to disable
202 tXAW
= Param
.Latency("X activation window")
203 activation_limit
= Param
.Unsigned("Max number of activates in window")
205 # time to exit power-down mode
206 # Exit power-down to next valid command delay
207 tXP
= Param
.Latency("0ns", "Power-up Delay")
209 # Exit Powerdown to commands requiring a locked DLL
210 tXPDLL
= Param
.Latency("0ns", "Power-up Delay with locked DLL")
212 # time to exit self-refresh mode
213 tXS
= Param
.Latency("0ns", "Self-refresh exit latency")
215 # time to exit self-refresh mode with locked DLL
216 tXSDLL
= Param
.Latency("0ns", "Self-refresh exit latency DLL")
218 # Currently rolled into other params
219 ######################################################################
221 # tRC - assumed to be tRAS + tRP
223 # Power Behaviour and Constraints
224 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
225 # defined as VDD and VDD2. Each current is defined for each voltage domain
226 # separately. For example, current IDD0 is active-precharge current for
227 # voltage domain VDD and current IDD02 is active-precharge current for
228 # voltage domain VDD2.
229 # By default all currents are set to 0mA. Users who are only interested in
230 # the performance of DRAMs can leave them at 0.
232 # Operating 1 Bank Active-Precharge current
233 IDD0
= Param
.Current("0mA", "Active precharge current")
235 # Operating 1 Bank Active-Precharge current multiple voltage Range
236 IDD02
= Param
.Current("0mA", "Active precharge current VDD2")
238 # Precharge Power-down Current: Slow exit
239 IDD2P0
= Param
.Current("0mA", "Precharge Powerdown slow")
241 # Precharge Power-down Current: Slow exit multiple voltage Range
242 IDD2P02
= Param
.Current("0mA", "Precharge Powerdown slow VDD2")
244 # Precharge Power-down Current: Fast exit
245 IDD2P1
= Param
.Current("0mA", "Precharge Powerdown fast")
247 # Precharge Power-down Current: Fast exit multiple voltage Range
248 IDD2P12
= Param
.Current("0mA", "Precharge Powerdown fast VDD2")
250 # Precharge Standby current
251 IDD2N
= Param
.Current("0mA", "Precharge Standby current")
253 # Precharge Standby current multiple voltage range
254 IDD2N2
= Param
.Current("0mA", "Precharge Standby current VDD2")
256 # Active Power-down current: slow exit
257 IDD3P0
= Param
.Current("0mA", "Active Powerdown slow")
259 # Active Power-down current: slow exit multiple voltage range
260 IDD3P02
= Param
.Current("0mA", "Active Powerdown slow VDD2")
262 # Active Power-down current : fast exit
263 IDD3P1
= Param
.Current("0mA", "Active Powerdown fast")
265 # Active Power-down current : fast exit multiple voltage range
266 IDD3P12
= Param
.Current("0mA", "Active Powerdown fast VDD2")
268 # Active Standby current
269 IDD3N
= Param
.Current("0mA", "Active Standby current")
271 # Active Standby current multiple voltage range
272 IDD3N2
= Param
.Current("0mA", "Active Standby current VDD2")
274 # Burst Read Operating Current
275 IDD4R
= Param
.Current("0mA", "READ current")
277 # Burst Read Operating Current multiple voltage range
278 IDD4R2
= Param
.Current("0mA", "READ current VDD2")
280 # Burst Write Operating Current
281 IDD4W
= Param
.Current("0mA", "WRITE current")
283 # Burst Write Operating Current multiple voltage range
284 IDD4W2
= Param
.Current("0mA", "WRITE current VDD2")
287 IDD5
= Param
.Current("0mA", "Refresh current")
289 # Refresh Current multiple voltage range
290 IDD52
= Param
.Current("0mA", "Refresh current VDD2")
292 # Self-Refresh Current
293 IDD6
= Param
.Current("0mA", "Self-refresh Current")
295 # Self-Refresh Current multiple voltage range
296 IDD62
= Param
.Current("0mA", "Self-refresh Current VDD2")
298 # Main voltage range of the DRAM
299 VDD
= Param
.Voltage("0V", "Main Voltage Range")
301 # Second voltage range defined by some DRAMs
302 VDD2
= Param
.Voltage("0V", "2nd Voltage Range")
304 # A single DDR3-1600 x64 channel (one command and address bus), with
305 # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
306 # an 8x8 configuration.
307 class DDR3_1600_x64(DRAMCtrl
):
308 # 8x8 configuration, 8 devices each with an 8-bit interface
311 # DDR3 is a BL8 device
314 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
315 device_rowbuffer_size
= '1kB'
317 # 8x8 configuration, so 8 devices
321 ranks_per_channel
= 2
323 # DDR3 has 8 banks in all configurations
329 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
344 # Greater of 4 CK or 7.5 ns
347 # Greater of 4 CK or 7.5 ns
350 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
353 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
356 # <=85C, half for >85C
359 # Current values from datasheet
368 # A single DDR3-2133 x64 channel refining a selected subset of the
369 # options for the DDR-1600 configuration, based on the same DDR3-1600
370 # 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
371 # consistent across the two configurations.
372 class DDR3_2133_x64(DDR3_1600_x64
):
376 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
387 # Current values from datasheet
396 # A single DDR4-2400 x64 channel (one command and address bus), with
397 # timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
398 # in an 8x8 configuration.
399 class DDR4_2400_x64(DRAMCtrl
):
400 # 8x8 configuration, 8 devices each with an 8-bit interface
403 # DDR4 is a BL8 device
406 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
407 device_rowbuffer_size
= '1kB'
409 # 8x8 configuration, so 8 devices
412 # Match our DDR3 configurations which is dual rank
413 ranks_per_channel
= 2
415 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
416 # Set to 4 for x4, x8 case
417 bank_groups_per_rank
= 4
419 # DDR4 has 16 banks (4 bank groups) in all
420 # configurations. Currently we do not capture the additional
421 # constraints incurred by the bank groups
427 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
428 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
429 # With bank group architectures, tBURST represents the CAS-to-CAS
430 # delay for bursts to different bank groups (tCCD_S)
433 # @2400 data rate, tCCD_L is 6 CK
434 # CAS-to-CAS delay for bursts to the same bank group
435 # tBURST is equivalent to tCCD_S; no explicit parameter required
436 # for CAS-to-CAS delay for bursts to different bank groups
445 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
448 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
457 # Here using the average of WTR_S and WTR_L
460 # Greater of 4 CK or 7.5 ns
463 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
466 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
469 # <=85C, half for >85C
472 # Current values from datasheet
484 # A single LPDDR2-S4 x32 interface (one command/address bus), with
485 # default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
486 # in a 1x32 configuration.
487 class LPDDR2_S4_1066_x32(DRAMCtrl
):
491 # 1x32 configuration, 1 device with a 32-bit interface
492 device_bus_width
= 32
494 # LPDDR2_S4 is a BL4 and BL8 device
497 # Each device has a page (row buffer) size of 1KB
498 # (this depends on the memory density)
499 device_rowbuffer_size
= '1kB'
501 # 1x32 configuration, so 1 device
505 ranks_per_channel
= 1
507 # LPDDR2-S4 has 8 banks in all configurations
516 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
519 # Pre-charge one bank 15 ns (all banks 18 ns)
527 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
528 # Note this is a BL8 DDR device.
529 # Requests larger than 32 bytes are broken down into multiple requests
537 # Irrespective of speed grade, tWTR is 7.5 ns
540 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
543 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
546 # Activate to activate irrespective of density and speed grade
549 # Irrespective of density, tFAW is 50 ns
553 # Current values from datasheet
569 # A single WideIO x128 interface (one command and address bus), with
570 # default timings based on an estimated WIO-200 8 Gbit part.
571 class WideIO_200_x128(DRAMCtrl
):
575 # 1x128 configuration, 1 device with a 128-bit interface
576 device_bus_width
= 128
578 # This is a BL4 device
581 # Each device has a page (row buffer) size of 4KB
582 # (this depends on the memory density)
583 device_rowbuffer_size
= '4kB'
585 # 1x128 configuration, so 1 device
588 # Use one rank for a one-high die stack
589 ranks_per_channel
= 1
591 # WideIO has 4 banks in all configurations
603 # Read to precharge is same as the burst
606 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
607 # Note this is a BL4 SDR device.
613 # WIO 8 Gb, <=85C, half for >85C
616 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
619 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
622 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
625 # Activate to activate irrespective of density and speed grade
628 # Two instead of four activation window
632 # The WideIO specification does not provide current information
634 # A single LPDDR3 x32 interface (one command/address bus), with
635 # default timings based on a LPDDR3-1600 4 Gbit part (Micron
636 # EDF8132A1MC) in a 1x32 configuration.
637 class LPDDR3_1600_x32(DRAMCtrl
):
641 # 1x32 configuration, 1 device with a 32-bit interface
642 device_bus_width
= 32
644 # LPDDR3 is a BL8 device
647 # Each device has a page (row buffer) size of 4KB
648 device_rowbuffer_size
= '4kB'
650 # 1x32 configuration, so 1 device
653 # Technically the datasheet is a dual-rank package, but for
654 # comparison with the LPDDR2 config we stick to a single rank
655 ranks_per_channel
= 1
657 # LPDDR3 has 8 banks in all configurations
665 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
671 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
674 # Pre-charge one bank 18 ns (all banks 21 ns)
677 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
678 # Note this is a BL8 DDR device.
679 # Requests larger than 32 bytes are broken down into multiple requests
687 # Irrespective of speed grade, tWTR is 7.5 ns
690 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
693 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
696 # Activate to activate irrespective of density and speed grade
699 # Irrespective of size, tFAW is 50 ns
703 # Current values from datasheet