1 # Copyright (c) 2012-2014 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2013 Amin Farmahini-Farahani
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
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23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 # Authors: Andreas Hansson
42 from m5
.params
import *
43 from AbstractMemory
import *
45 # Enum for memory scheduling algorithms, currently First-Come
46 # First-Served and a First-Row Hit then First-Come First-Served
47 class MemSched(Enum
): vals
= ['fcfs', 'frfcfs']
49 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
50 # channel, rank, bank, row and column, respectively, and going from
51 # MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
52 # suitable for an open-page policy, optimising for sequential accesses
53 # hitting in the open row. For a closed-page policy, RoCoRaBaCh
54 # maximises parallelism.
55 class AddrMap(Enum
): vals
= ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
57 # Enum for the page policy, either open, open_adaptive, close, or
59 class PageManage(Enum
): vals
= ['open', 'open_adaptive', 'close',
62 # DRAMCtrl is a single-channel single-ported DRAM controller model
63 # that aims to model the most important system-level performance
64 # effects of a DRAM without getting into too much detail of the DRAM
66 class DRAMCtrl(AbstractMemory
):
68 cxx_header
= "mem/dram_ctrl.hh"
70 # single-ported on the system interface side, instantiate with a
71 # bus in front of the controller for multiple ports
72 port
= SlavePort("Slave port")
74 # the basic configuration of the controller architecture, note
75 # that each entry corresponds to a burst for the specific DRAM
76 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
77 # the cacheline size or request/packet size
78 write_buffer_size
= Param
.Unsigned(64, "Number of write queue entries")
79 read_buffer_size
= Param
.Unsigned(32, "Number of read queue entries")
81 # threshold in percent for when to forcefully trigger writes and
82 # start emptying the write buffer
83 write_high_thresh_perc
= Param
.Percent(85, "Threshold to force writes")
85 # threshold in percentage for when to start writes if the read
87 write_low_thresh_perc
= Param
.Percent(50, "Threshold to start writes")
89 # minimum write bursts to schedule before switching back to reads
90 min_writes_per_switch
= Param
.Unsigned(16, "Minimum write bursts before "
93 # scheduler, address map and page policy
94 mem_sched_policy
= Param
.MemSched('frfcfs', "Memory scheduling policy")
95 addr_mapping
= Param
.AddrMap('RoRaBaChCo', "Address mapping policy")
96 page_policy
= Param
.PageManage('open_adaptive', "Page management policy")
98 # enforce a limit on the number of accesses per row
99 max_accesses_per_row
= Param
.Unsigned(16, "Max accesses per row before "
102 # size of DRAM Chip in Bytes
103 device_size
= Param
.MemorySize("Size of DRAM chip")
105 # pipeline latency of the controller and PHY, split into a
106 # frontend part and a backend part, with reads and writes serviced
107 # by the queues only seeing the frontend contribution, and reads
108 # serviced by the memory seeing the sum of the two
109 static_frontend_latency
= Param
.Latency("10ns", "Static frontend latency")
110 static_backend_latency
= Param
.Latency("10ns", "Static backend latency")
112 # the physical organisation of the DRAM
113 device_bus_width
= Param
.Unsigned("data bus width in bits for each DRAM "\
115 burst_length
= Param
.Unsigned("Burst lenght (BL) in beats")
116 device_rowbuffer_size
= Param
.MemorySize("Page (row buffer) size per "\
118 devices_per_rank
= Param
.Unsigned("Number of devices/chips per rank")
119 ranks_per_channel
= Param
.Unsigned("Number of ranks per channel")
121 # default to 0 bank groups per rank, indicating bank group architecture
123 # update per memory class when bank group architecture is supported
124 bank_groups_per_rank
= Param
.Unsigned(0, "Number of bank groups per rank")
125 banks_per_rank
= Param
.Unsigned("Number of banks per rank")
126 # only used for the address mapping as the controller by
127 # construction is a single channel and multiple controllers have
128 # to be instantiated for a multi-channel configuration
129 channels
= Param
.Unsigned(1, "Number of channels")
131 # For power modelling we need to know if the DRAM has a DLL or not
132 dll
= Param
.Bool(True, "DRAM has DLL or not")
134 # DRAMPower provides in addition to the core power, the possibility to
135 # include RD/WR termination and IO power. This calculation assumes some
136 # default values. The integration of DRAMPower with gem5 does not include
137 # IO and RD/WR termination power by default. This might be added as an
138 # additional feature in the future.
140 # timing behaviour and constraints - all in nanoseconds
142 # the base clock period of the DRAM
143 tCK
= Param
.Latency("Clock period")
145 # the amount of time in nanoseconds from issuing an activate command
146 # to the data being available in the row buffer for a read/write
147 tRCD
= Param
.Latency("RAS to CAS delay")
149 # the time from issuing a read/write command to seeing the actual data
150 tCL
= Param
.Latency("CAS latency")
152 # minimum time between a precharge and subsequent activate
153 tRP
= Param
.Latency("Row precharge time")
155 # minimum time between an activate and a precharge to the same row
156 tRAS
= Param
.Latency("ACT to PRE delay")
158 # minimum time between a write data transfer and a precharge
159 tWR
= Param
.Latency("Write recovery time")
161 # minimum time between a read and precharge command
162 tRTP
= Param
.Latency("Read to precharge")
164 # time to complete a burst transfer, typically the burst length
165 # divided by two due to the DDR bus, but by making it a parameter
166 # it is easier to also evaluate SDR memories like WideIO.
167 # This parameter has to account for burst length.
168 # Read/Write requests with data size larger than one full burst are broken
169 # down into multiple requests in the controller
170 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
171 # With bank group architectures, tBURST represents the CAS-to-CAS
172 # delay for bursts to different bank groups (tCCD_S)
173 tBURST
= Param
.Latency("Burst duration (for DDR burst length / 2 cycles)")
175 # CAS-to-CAS delay for bursts to the same bank group
176 # only utilized with bank group architectures; set to 0 for default case
177 # tBURST is equivalent to tCCD_S; no explicit parameter required
178 # for CAS-to-CAS delay for bursts to different bank groups
179 tCCD_L
= Param
.Latency("0ns", "Same bank group CAS to CAS delay")
181 # time taken to complete one refresh cycle (N rows in all banks)
182 tRFC
= Param
.Latency("Refresh cycle time")
184 # refresh command interval, how often a "ref" command needs
185 # to be sent. It is 7.8 us for a 64ms refresh requirement
186 tREFI
= Param
.Latency("Refresh command interval")
188 # write-to-read, same rank turnaround penalty
189 tWTR
= Param
.Latency("Write to read, same rank switching time")
191 # read-to-write, same rank turnaround penalty
192 tRTW
= Param
.Latency("Read to write, same rank switching time")
194 # rank-to-rank bus delay penalty
195 # this does not correlate to a memory timing parameter and encompasses:
196 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
197 # different rank bus delay
198 tCS
= Param
.Latency("Rank to rank switching time")
200 # minimum row activate to row activate delay time
201 tRRD
= Param
.Latency("ACT to ACT delay")
203 # only utilized with bank group architectures; set to 0 for default case
204 tRRD_L
= Param
.Latency("0ns", "Same bank group ACT to ACT delay")
206 # time window in which a maximum number of activates are allowed
207 # to take place, set to 0 to disable
208 tXAW
= Param
.Latency("X activation window")
209 activation_limit
= Param
.Unsigned("Max number of activates in window")
211 # time to exit power-down mode
212 # Exit power-down to next valid command delay
213 tXP
= Param
.Latency("0ns", "Power-up Delay")
215 # Exit Powerdown to commands requiring a locked DLL
216 tXPDLL
= Param
.Latency("0ns", "Power-up Delay with locked DLL")
218 # time to exit self-refresh mode
219 tXS
= Param
.Latency("0ns", "Self-refresh exit latency")
221 # time to exit self-refresh mode with locked DLL
222 tXSDLL
= Param
.Latency("0ns", "Self-refresh exit latency DLL")
224 # Currently rolled into other params
225 ######################################################################
227 # tRC - assumed to be tRAS + tRP
229 # Power Behaviour and Constraints
230 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
231 # defined as VDD and VDD2. Each current is defined for each voltage domain
232 # separately. For example, current IDD0 is active-precharge current for
233 # voltage domain VDD and current IDD02 is active-precharge current for
234 # voltage domain VDD2.
235 # By default all currents are set to 0mA. Users who are only interested in
236 # the performance of DRAMs can leave them at 0.
238 # Operating 1 Bank Active-Precharge current
239 IDD0
= Param
.Current("0mA", "Active precharge current")
241 # Operating 1 Bank Active-Precharge current multiple voltage Range
242 IDD02
= Param
.Current("0mA", "Active precharge current VDD2")
244 # Precharge Power-down Current: Slow exit
245 IDD2P0
= Param
.Current("0mA", "Precharge Powerdown slow")
247 # Precharge Power-down Current: Slow exit multiple voltage Range
248 IDD2P02
= Param
.Current("0mA", "Precharge Powerdown slow VDD2")
250 # Precharge Power-down Current: Fast exit
251 IDD2P1
= Param
.Current("0mA", "Precharge Powerdown fast")
253 # Precharge Power-down Current: Fast exit multiple voltage Range
254 IDD2P12
= Param
.Current("0mA", "Precharge Powerdown fast VDD2")
256 # Precharge Standby current
257 IDD2N
= Param
.Current("0mA", "Precharge Standby current")
259 # Precharge Standby current multiple voltage range
260 IDD2N2
= Param
.Current("0mA", "Precharge Standby current VDD2")
262 # Active Power-down current: slow exit
263 IDD3P0
= Param
.Current("0mA", "Active Powerdown slow")
265 # Active Power-down current: slow exit multiple voltage range
266 IDD3P02
= Param
.Current("0mA", "Active Powerdown slow VDD2")
268 # Active Power-down current : fast exit
269 IDD3P1
= Param
.Current("0mA", "Active Powerdown fast")
271 # Active Power-down current : fast exit multiple voltage range
272 IDD3P12
= Param
.Current("0mA", "Active Powerdown fast VDD2")
274 # Active Standby current
275 IDD3N
= Param
.Current("0mA", "Active Standby current")
277 # Active Standby current multiple voltage range
278 IDD3N2
= Param
.Current("0mA", "Active Standby current VDD2")
280 # Burst Read Operating Current
281 IDD4R
= Param
.Current("0mA", "READ current")
283 # Burst Read Operating Current multiple voltage range
284 IDD4R2
= Param
.Current("0mA", "READ current VDD2")
286 # Burst Write Operating Current
287 IDD4W
= Param
.Current("0mA", "WRITE current")
289 # Burst Write Operating Current multiple voltage range
290 IDD4W2
= Param
.Current("0mA", "WRITE current VDD2")
293 IDD5
= Param
.Current("0mA", "Refresh current")
295 # Refresh Current multiple voltage range
296 IDD52
= Param
.Current("0mA", "Refresh current VDD2")
298 # Self-Refresh Current
299 IDD6
= Param
.Current("0mA", "Self-refresh Current")
301 # Self-Refresh Current multiple voltage range
302 IDD62
= Param
.Current("0mA", "Self-refresh Current VDD2")
304 # Main voltage range of the DRAM
305 VDD
= Param
.Voltage("0V", "Main Voltage Range")
307 # Second voltage range defined by some DRAMs
308 VDD2
= Param
.Voltage("0V", "2nd Voltage Range")
310 # A single DDR3-1600 x64 channel (one command and address bus), with
311 # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
312 # an 8x8 configuration.
313 class DDR3_1600_x64(DRAMCtrl
):
314 # size of device in bytes
315 device_size
= '512MB'
317 # 8x8 configuration, 8 devices each with an 8-bit interface
320 # DDR3 is a BL8 device
323 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
324 device_rowbuffer_size
= '1kB'
326 # 8x8 configuration, so 8 devices
330 ranks_per_channel
= 2
332 # DDR3 has 8 banks in all configurations
338 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
353 # Greater of 4 CK or 7.5 ns
356 # Greater of 4 CK or 7.5 ns
359 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
362 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
365 # <=85C, half for >85C
368 # Current values from datasheet
377 # A single DDR3-2133 x64 channel refining a selected subset of the
378 # options for the DDR-1600 configuration, based on the same DDR3-1600
379 # 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
380 # consistent across the two configurations.
381 class DDR3_2133_x64(DDR3_1600_x64
):
385 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
396 # Current values from datasheet
405 # A single DDR4-2400 x64 channel (one command and address bus), with
406 # timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
407 # in an 8x8 configuration.
408 class DDR4_2400_x64(DRAMCtrl
):
410 device_size
= '512MB'
412 # 8x8 configuration, 8 devices each with an 8-bit interface
415 # DDR4 is a BL8 device
418 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
419 device_rowbuffer_size
= '1kB'
421 # 8x8 configuration, so 8 devices
424 # Match our DDR3 configurations which is dual rank
425 ranks_per_channel
= 2
427 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
428 # Set to 4 for x4, x8 case
429 bank_groups_per_rank
= 4
431 # DDR4 has 16 banks (4 bank groups) in all
432 # configurations. Currently we do not capture the additional
433 # constraints incurred by the bank groups
439 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
440 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
441 # With bank group architectures, tBURST represents the CAS-to-CAS
442 # delay for bursts to different bank groups (tCCD_S)
445 # @2400 data rate, tCCD_L is 6 CK
446 # CAS-to-CAS delay for bursts to the same bank group
447 # tBURST is equivalent to tCCD_S; no explicit parameter required
448 # for CAS-to-CAS delay for bursts to different bank groups
457 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
460 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
469 # Here using the average of WTR_S and WTR_L
472 # Greater of 4 CK or 7.5 ns
475 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
478 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
481 # <=85C, half for >85C
484 # Current values from datasheet
496 # A single LPDDR2-S4 x32 interface (one command/address bus), with
497 # default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
498 # in a 1x32 configuration.
499 class LPDDR2_S4_1066_x32(DRAMCtrl
):
504 device_size
= '512MB'
506 # 1x32 configuration, 1 device with a 32-bit interface
507 device_bus_width
= 32
509 # LPDDR2_S4 is a BL4 and BL8 device
512 # Each device has a page (row buffer) size of 1KB
513 # (this depends on the memory density)
514 device_rowbuffer_size
= '1kB'
516 # 1x32 configuration, so 1 device
520 ranks_per_channel
= 1
522 # LPDDR2-S4 has 8 banks in all configurations
531 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
534 # Pre-charge one bank 15 ns (all banks 18 ns)
542 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
543 # Note this is a BL8 DDR device.
544 # Requests larger than 32 bytes are broken down into multiple requests
552 # Irrespective of speed grade, tWTR is 7.5 ns
555 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
558 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
561 # Activate to activate irrespective of density and speed grade
564 # Irrespective of density, tFAW is 50 ns
568 # Current values from datasheet
584 # A single WideIO x128 interface (one command and address bus), with
585 # default timings based on an estimated WIO-200 8 Gbit part.
586 class WideIO_200_x128(DRAMCtrl
):
591 device_size
= '1024MB'
593 # 1x128 configuration, 1 device with a 128-bit interface
594 device_bus_width
= 128
596 # This is a BL4 device
599 # Each device has a page (row buffer) size of 4KB
600 # (this depends on the memory density)
601 device_rowbuffer_size
= '4kB'
603 # 1x128 configuration, so 1 device
606 # Use one rank for a one-high die stack
607 ranks_per_channel
= 1
609 # WideIO has 4 banks in all configurations
621 # Read to precharge is same as the burst
624 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
625 # Note this is a BL4 SDR device.
631 # WIO 8 Gb, <=85C, half for >85C
634 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
637 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
640 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
643 # Activate to activate irrespective of density and speed grade
646 # Two instead of four activation window
650 # The WideIO specification does not provide current information
652 # A single LPDDR3 x32 interface (one command/address bus), with
653 # default timings based on a LPDDR3-1600 4 Gbit part (Micron
654 # EDF8132A1MC) in a 1x32 configuration.
655 class LPDDR3_1600_x32(DRAMCtrl
):
660 device_size
= '512MB'
662 # 1x32 configuration, 1 device with a 32-bit interface
663 device_bus_width
= 32
665 # LPDDR3 is a BL8 device
668 # Each device has a page (row buffer) size of 4KB
669 device_rowbuffer_size
= '4kB'
671 # 1x32 configuration, so 1 device
674 # Technically the datasheet is a dual-rank package, but for
675 # comparison with the LPDDR2 config we stick to a single rank
676 ranks_per_channel
= 1
678 # LPDDR3 has 8 banks in all configurations
686 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
692 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
695 # Pre-charge one bank 18 ns (all banks 21 ns)
698 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
699 # Note this is a BL8 DDR device.
700 # Requests larger than 32 bytes are broken down into multiple requests
708 # Irrespective of speed grade, tWTR is 7.5 ns
711 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
714 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
717 # Activate to activate irrespective of density and speed grade
720 # Irrespective of size, tFAW is 50 ns
724 # Current values from datasheet
740 # A single GDDR5 x64 interface, with
741 # default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
742 # H5GQ1H24AFR) in a 2x32 configuration.
743 class GDDR5_4000_x64(DRAMCtrl
):
745 device_size
= '128MB'
747 # 2x32 configuration, 1 device with a 32-bit interface
748 device_bus_width
= 32
750 # GDDR5 is a BL8 device
753 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
754 device_rowbuffer_size
= '256B'
756 # 2x32 configuration, so 2 devices
760 ranks_per_channel
= 1
762 # GDDR5 has 4 bank groups
763 bank_groups_per_rank
= 4
765 # GDDR5 has 16 banks with 4 bank groups
771 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
772 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
773 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
774 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
775 # With bank group architectures, tBURST represents the CAS-to-CAS
776 # delay for bursts to different bank groups (tCCD_S)
779 # @1000MHz data rate, tCCD_L is 3 CK
780 # CAS-to-CAS delay for bursts to the same bank group
781 # tBURST is equivalent to tCCD_S; no explicit parameter required
782 # for CAS-to-CAS delay for bursts to different bank groups
787 # tCL is not directly found in datasheet and assumed equal tRCD
793 # RRD_S (different bank group)
794 # RRD_S is 5.5 ns in datasheet.
795 # rounded to the next multiple of tCK
798 # RRD_L (same bank group)
799 # RRD_L is 5.5 ns in datasheet.
800 # rounded to the next multiple of tCK
806 # Therefore, activation limit is set to 0
812 # Here using the average of WTR_S and WTR_L
815 # Read-to-Precharge 2 CK
821 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns