1 # Copyright (c) 2012-2014 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
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9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2013 Amin Farmahini-Farahani
14 # All rights reserved.
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17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
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25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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39 # Authors: Andreas Hansson
42 from m5
.params
import *
43 from AbstractMemory
import *
45 # Enum for memory scheduling algorithms, currently First-Come
46 # First-Served and a First-Row Hit then First-Come First-Served
47 class MemSched(Enum
): vals
= ['fcfs', 'frfcfs']
49 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
50 # channel, rank, bank, row and column, respectively, and going from
51 # MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
52 # suitable for an open-page policy, optimising for sequential accesses
53 # hitting in the open row. For a closed-page policy, RoCoRaBaCh
54 # maximises parallelism.
55 class AddrMap(Enum
): vals
= ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
57 # Enum for the page policy, either open, open_adaptive, close, or
59 class PageManage(Enum
): vals
= ['open', 'open_adaptive', 'close',
62 # DRAMCtrl is a single-channel single-ported DRAM controller model
63 # that aims to model the most important system-level performance
64 # effects of a DRAM without getting into too much detail of the DRAM
66 class DRAMCtrl(AbstractMemory
):
68 cxx_header
= "mem/dram_ctrl.hh"
70 # single-ported on the system interface side, instantiate with a
71 # bus in front of the controller for multiple ports
72 port
= SlavePort("Slave port")
74 # the basic configuration of the controller architecture
75 write_buffer_size
= Param
.Unsigned(64, "Number of write queue entries")
76 read_buffer_size
= Param
.Unsigned(32, "Number of read queue entries")
78 # threshold in percent for when to forcefully trigger writes and
79 # start emptying the write buffer
80 write_high_thresh_perc
= Param
.Percent(85, "Threshold to force writes")
82 # threshold in percentage for when to start writes if the read
84 write_low_thresh_perc
= Param
.Percent(50, "Threshold to start writes")
86 # minimum write bursts to schedule before switching back to reads
87 min_writes_per_switch
= Param
.Unsigned(16, "Minimum write bursts before "
90 # scheduler, address map and page policy
91 mem_sched_policy
= Param
.MemSched('frfcfs', "Memory scheduling policy")
92 addr_mapping
= Param
.AddrMap('RoRaBaChCo', "Address mapping policy")
93 page_policy
= Param
.PageManage('open_adaptive', "Page management policy")
95 # enforce a limit on the number of accesses per row
96 max_accesses_per_row
= Param
.Unsigned(16, "Max accesses per row before "
99 # pipeline latency of the controller and PHY, split into a
100 # frontend part and a backend part, with reads and writes serviced
101 # by the queues only seeing the frontend contribution, and reads
102 # serviced by the memory seeing the sum of the two
103 static_frontend_latency
= Param
.Latency("10ns", "Static frontend latency")
104 static_backend_latency
= Param
.Latency("10ns", "Static backend latency")
106 # the physical organisation of the DRAM
107 device_bus_width
= Param
.Unsigned("data bus width in bits for each DRAM "\
109 burst_length
= Param
.Unsigned("Burst lenght (BL) in beats")
110 device_rowbuffer_size
= Param
.MemorySize("Page (row buffer) size per "\
112 devices_per_rank
= Param
.Unsigned("Number of devices/chips per rank")
113 ranks_per_channel
= Param
.Unsigned("Number of ranks per channel")
114 banks_per_rank
= Param
.Unsigned("Number of banks per rank")
115 # only used for the address mapping as the controller by
116 # construction is a single channel and multiple controllers have
117 # to be instantiated for a multi-channel configuration
118 channels
= Param
.Unsigned(1, "Number of channels")
120 # timing behaviour and constraints - all in nanoseconds
122 # the amount of time in nanoseconds from issuing an activate command
123 # to the data being available in the row buffer for a read/write
124 tRCD
= Param
.Latency("RAS to CAS delay")
126 # the time from issuing a read/write command to seeing the actual data
127 tCL
= Param
.Latency("CAS latency")
129 # minimum time between a precharge and subsequent activate
130 tRP
= Param
.Latency("Row precharge time")
132 # minimum time between an activate and a precharge to the same row
133 tRAS
= Param
.Latency("ACT to PRE delay")
135 # minimum time between a write data transfer and a precharge
136 tWR
= Param
.Latency("Write recovery time")
138 # minimum time between a read and precharge command
139 tRTP
= Param
.Latency("Read to precharge")
141 # time to complete a burst transfer, typically the burst length
142 # divided by two due to the DDR bus, but by making it a parameter
143 # it is easier to also evaluate SDR memories like WideIO.
144 # This parameter has to account for burst length.
145 # Read/Write requests with data size larger than one full burst are broken
146 # down into multiple requests in the controller
147 tBURST
= Param
.Latency("Burst duration (for DDR burst length / 2 cycles)")
149 # time taken to complete one refresh cycle (N rows in all banks)
150 tRFC
= Param
.Latency("Refresh cycle time")
152 # refresh command interval, how often a "ref" command needs
153 # to be sent. It is 7.8 us for a 64ms refresh requirement
154 tREFI
= Param
.Latency("Refresh command interval")
156 # write-to-read turn around penalty
157 tWTR
= Param
.Latency("Write to read switching time")
159 # read-to-write turn around penalty, bus turnaround delay
160 tRTW
= Param
.Latency("Read to write switching time")
162 # minimum row activate to row activate delay time
163 tRRD
= Param
.Latency("ACT to ACT delay")
165 # time window in which a maximum number of activates are allowed
166 # to take place, set to 0 to disable
167 tXAW
= Param
.Latency("X activation window")
168 activation_limit
= Param
.Unsigned("Max number of activates in window")
170 # Currently rolled into other params
171 ######################################################################
173 # tRC - assumed to be tRAS + tRP
175 # A single DDR3 x64 interface (one command and address bus), with
176 # default timings based on DDR3-1600 4 Gbit parts in an 8x8
177 # configuration, which would amount to 4 Gbyte of memory.
178 class DDR3_1600_x64(DRAMCtrl
):
179 # 8x8 configuration, 8 devices each with an 8-bit interface
182 # DDR3 is a BL8 device
185 # Each device has a page (row buffer) size of 1KB
186 # (this depends on the memory density)
187 device_rowbuffer_size
= '1kB'
189 # 8x8 configuration, so 8 devices
193 ranks_per_channel
= 2
195 # DDR3 has 8 banks in all configurations
198 # DDR3-1600 11-11-11-28
206 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz.
207 # Note this is a BL8 DDR device.
210 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns
213 # DDR3, <=85C, half for >85C
216 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
219 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
222 # Assume 5 CK for activate to activate for different banks
225 # With a 2kbyte page size, DDR3-1600 lands around 40 ns
230 # A single DDR3 x64 interface (one command and address bus), with
231 # default timings based on DDR3-1333 4 Gbit parts in an 8x8
232 # configuration, which would amount to 4 GByte of memory. This
233 # configuration is primarily for comparing with DRAMSim2, and all the
234 # parameters except ranks_per_channel are based on the DRAMSim2 config
235 # file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has
236 # to be manually set, depending on size of the memory to be
237 # simulated. By default DRAMSim2 has 2048MB of memory with a single
238 # rank. Therefore for 4 GByte memory, set ranks_per_channel = 2
239 class DDR3_1333_x64_DRAMSim2(DRAMCtrl
):
240 # 8x8 configuration, 8 devices each with an 8-bit interface
243 # DDR3 is a BL8 device
246 # Each device has a page (row buffer) size of 1KB
247 # (this depends on the memory density)
248 device_rowbuffer_size
= '1kB'
250 # 8x8 configuration, so 8 devices
254 ranks_per_channel
= 2
256 # DDR3 has 8 banks in all configurations
266 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz.
267 # Note this is a BL8 DDR device.
272 # DDR3, <=85C, half for >85C
275 # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns
278 # Default read-to-write bus around to 2 CK, @666.66 MHz = 3 ns
287 # A single LPDDR2-S4 x32 interface (one command/address bus), with
288 # default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
290 class LPDDR2_S4_1066_x32(DRAMCtrl
):
291 # 1x32 configuration, 1 device with a 32-bit interface
292 device_bus_width
= 32
294 # LPDDR2_S4 is a BL4 and BL8 device
297 # Each device has a page (row buffer) size of 1KB
298 # (this depends on the memory density)
299 device_rowbuffer_size
= '1kB'
301 # 1x32 configuration, so 1 device
305 ranks_per_channel
= 1
307 # LPDDR2-S4 has 8 banks in all configurations
313 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
316 # Pre-charge one bank 15 ns (all banks 18 ns)
322 # 6 CK read to precharge delay
325 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
326 # Note this is a BL8 DDR device.
327 # Requests larger than 32 bytes are broken down into multiple requests
335 # Irrespective of speed grade, tWTR is 7.5 ns
338 # Default read-to-write bus around to 2 CK, @533 MHz = 3.75 ns
341 # Activate to activate irrespective of density and speed grade
344 # Irrespective of density, tFAW is 50 ns
348 # A single WideIO x128 interface (one command and address bus), with
349 # default timings based on an estimated WIO-200 8 Gbit part.
350 class WideIO_200_x128(DRAMCtrl
):
351 # 1x128 configuration, 1 device with a 128-bit interface
352 device_bus_width
= 128
354 # This is a BL4 device
357 # Each device has a page (row buffer) size of 4KB
358 # (this depends on the memory density)
359 device_rowbuffer_size
= '4kB'
361 # 1x128 configuration, so 1 device
364 # Use one rank for a one-high die stack
365 ranks_per_channel
= 1
367 # WideIO has 4 banks in all configurations
376 # Read to precharge is same as the burst
379 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
380 # Note this is a BL4 SDR device.
386 # WIO 8 Gb, <=85C, half for >85C
389 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
392 # Default read-to-write bus around to 2 CK, @200 MHz = 10 ns
395 # Activate to activate irrespective of density and speed grade
398 # Two instead of four activation window
402 # A single LPDDR3 x32 interface (one command/address bus), with
403 # default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
405 class LPDDR3_1600_x32(DRAMCtrl
):
406 # 1x32 configuration, 1 device with a 32-bit interface
407 device_bus_width
= 32
409 # LPDDR3 is a BL8 device
412 # Each device has a page (row buffer) size of 4KB
413 device_rowbuffer_size
= '4kB'
415 # 1x32 configuration, so 1 device
419 ranks_per_channel
= 1
421 # LPDDR3 has 8 banks in all configurations
427 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
433 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
436 # Pre-charge one bank 15 ns (all banks 18 ns)
439 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
440 # Note this is a BL8 DDR device.
441 # Requests larger than 32 bytes are broken down into multiple requests
449 # Irrespective of speed grade, tWTR is 7.5 ns
452 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
455 # Activate to activate irrespective of density and speed grade
458 # Irrespective of size, tFAW is 50 ns