1 # Copyright (c) 2012-2014 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2013 Amin Farmahini-Farahani
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
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24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 # Authors: Andreas Hansson
42 from m5
.params
import *
43 from AbstractMemory
import *
45 # Enum for memory scheduling algorithms, currently First-Come
46 # First-Served and a First-Row Hit then First-Come First-Served
47 class MemSched(Enum
): vals
= ['fcfs', 'frfcfs']
49 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
50 # channel, rank, bank, row and column, respectively, and going from
51 # MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
52 # suitable for an open-page policy, optimising for sequential accesses
53 # hitting in the open row. For a closed-page policy, RoCoRaBaCh
54 # maximises parallelism.
55 class AddrMap(Enum
): vals
= ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
57 # Enum for the page policy, either open, open_adaptive, close, or
59 class PageManage(Enum
): vals
= ['open', 'open_adaptive', 'close',
62 # DRAMCtrl is a single-channel single-ported DRAM controller model
63 # that aims to model the most important system-level performance
64 # effects of a DRAM without getting into too much detail of the DRAM
66 class DRAMCtrl(AbstractMemory
):
68 cxx_header
= "mem/dram_ctrl.hh"
70 # single-ported on the system interface side, instantiate with a
71 # bus in front of the controller for multiple ports
72 port
= SlavePort("Slave port")
74 # the basic configuration of the controller architecture
75 write_buffer_size
= Param
.Unsigned(64, "Number of write queue entries")
76 read_buffer_size
= Param
.Unsigned(32, "Number of read queue entries")
78 # threshold in percent for when to forcefully trigger writes and
79 # start emptying the write buffer
80 write_high_thresh_perc
= Param
.Percent(85, "Threshold to force writes")
82 # threshold in percentage for when to start writes if the read
84 write_low_thresh_perc
= Param
.Percent(50, "Threshold to start writes")
86 # minimum write bursts to schedule before switching back to reads
87 min_writes_per_switch
= Param
.Unsigned(16, "Minimum write bursts before "
90 # scheduler, address map and page policy
91 mem_sched_policy
= Param
.MemSched('frfcfs', "Memory scheduling policy")
92 addr_mapping
= Param
.AddrMap('RoRaBaChCo', "Address mapping policy")
93 page_policy
= Param
.PageManage('open_adaptive', "Page management policy")
95 # enforce a limit on the number of accesses per row
96 max_accesses_per_row
= Param
.Unsigned(16, "Max accesses per row before "
99 # pipeline latency of the controller and PHY, split into a
100 # frontend part and a backend part, with reads and writes serviced
101 # by the queues only seeing the frontend contribution, and reads
102 # serviced by the memory seeing the sum of the two
103 static_frontend_latency
= Param
.Latency("10ns", "Static frontend latency")
104 static_backend_latency
= Param
.Latency("10ns", "Static backend latency")
106 # the physical organisation of the DRAM
107 device_bus_width
= Param
.Unsigned("data bus width in bits for each DRAM "\
109 burst_length
= Param
.Unsigned("Burst lenght (BL) in beats")
110 device_rowbuffer_size
= Param
.MemorySize("Page (row buffer) size per "\
112 devices_per_rank
= Param
.Unsigned("Number of devices/chips per rank")
113 ranks_per_channel
= Param
.Unsigned("Number of ranks per channel")
115 # default to 0 bank groups per rank, indicating bank group architecture
117 # update per memory class when bank group architecture is supported
118 bank_groups_per_rank
= Param
.Unsigned(0, "Number of bank groups per rank")
119 banks_per_rank
= Param
.Unsigned("Number of banks per rank")
120 # only used for the address mapping as the controller by
121 # construction is a single channel and multiple controllers have
122 # to be instantiated for a multi-channel configuration
123 channels
= Param
.Unsigned(1, "Number of channels")
125 # timing behaviour and constraints - all in nanoseconds
127 # the base clock period of the DRAM
128 tCK
= Param
.Latency("Clock period")
130 # the amount of time in nanoseconds from issuing an activate command
131 # to the data being available in the row buffer for a read/write
132 tRCD
= Param
.Latency("RAS to CAS delay")
134 # the time from issuing a read/write command to seeing the actual data
135 tCL
= Param
.Latency("CAS latency")
137 # minimum time between a precharge and subsequent activate
138 tRP
= Param
.Latency("Row precharge time")
140 # minimum time between an activate and a precharge to the same row
141 tRAS
= Param
.Latency("ACT to PRE delay")
143 # minimum time between a write data transfer and a precharge
144 tWR
= Param
.Latency("Write recovery time")
146 # minimum time between a read and precharge command
147 tRTP
= Param
.Latency("Read to precharge")
149 # time to complete a burst transfer, typically the burst length
150 # divided by two due to the DDR bus, but by making it a parameter
151 # it is easier to also evaluate SDR memories like WideIO.
152 # This parameter has to account for burst length.
153 # Read/Write requests with data size larger than one full burst are broken
154 # down into multiple requests in the controller
155 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
156 # With bank group architectures, tBURST represents the CAS-to-CAS
157 # delay for bursts to different bank groups (tCCD_S)
158 tBURST
= Param
.Latency("Burst duration (for DDR burst length / 2 cycles)")
160 # CAS-to-CAS delay for bursts to the same bank group
161 # only utilized with bank group architectures; set to 0 for default case
162 # tBURST is equivalent to tCCD_S; no explicit parameter required
163 # for CAS-to-CAS delay for bursts to different bank groups
164 tCCD_L
= Param
.Latency("0ns", "Same bank group CAS to CAS delay")
166 # time taken to complete one refresh cycle (N rows in all banks)
167 tRFC
= Param
.Latency("Refresh cycle time")
169 # refresh command interval, how often a "ref" command needs
170 # to be sent. It is 7.8 us for a 64ms refresh requirement
171 tREFI
= Param
.Latency("Refresh command interval")
173 # write-to-read, same rank turnaround penalty
174 tWTR
= Param
.Latency("Write to read, same rank switching time")
176 # read-to-write, same rank turnaround penalty
177 tRTW
= Param
.Latency("Read to write, same rank switching time")
179 # rank-to-rank bus delay penalty
180 # this does not correlate to a memory timing parameter and encompasses:
181 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
182 # different rank bus delay
183 tCS
= Param
.Latency("Rank to rank switching time")
185 # minimum row activate to row activate delay time
186 tRRD
= Param
.Latency("ACT to ACT delay")
188 # only utilized with bank group architectures; set to 0 for default case
189 tRRD_L
= Param
.Latency("0ns", "Same bank group ACT to ACT delay")
191 # time window in which a maximum number of activates are allowed
192 # to take place, set to 0 to disable
193 tXAW
= Param
.Latency("X activation window")
194 activation_limit
= Param
.Unsigned("Max number of activates in window")
196 # Currently rolled into other params
197 ######################################################################
199 # tRC - assumed to be tRAS + tRP
201 # A single DDR3-1600 x64 channel (one command and address bus), with
202 # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
203 # an 8x8 configuration, amounting to 4 Gbyte of memory.
204 class DDR3_1600_x64(DRAMCtrl
):
205 # 8x8 configuration, 8 devices each with an 8-bit interface
208 # DDR3 is a BL8 device
211 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
212 device_rowbuffer_size
= '1kB'
214 # 8x8 configuration, so 8 devices
218 ranks_per_channel
= 2
220 # DDR3 has 8 banks in all configurations
226 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
241 # Greater of 4 CK or 7.5 ns
244 # Greater of 4 CK or 7.5 ns
247 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
250 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
253 # <=85C, half for >85C
256 # A single DDR3-2133 x64 channel refining a selected subset of the
257 # options for the DDR-1600 configuration, based on the same DDR3-1600
258 # 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
259 # consistent across the two configurations.
260 class DDR3_2133_x64(DDR3_1600_x64
):
264 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
275 # A single DDR4-2400 x64 channel (one command and address bus), with
276 # timings based on a DDR4-2400 4 Gbit datasheet (Samsung K4A4G085WD)
277 # in an 8x8 configuration, amounting to 4 Gbyte of memory.
278 class DDR4_2400_x64(DRAMCtrl
):
279 # 8x8 configuration, 8 devices each with an 8-bit interface
282 # DDR4 is a BL8 device
285 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
286 device_rowbuffer_size
= '1kB'
288 # 8x8 configuration, so 8 devices
292 ranks_per_channel
= 1
294 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
295 # Set to 4 for x4, x8 case
296 bank_groups_per_rank
= 4
298 # DDR4 has 16 banks (4 bank groups) in all
299 # configurations. Currently we do not capture the additional
300 # constraints incurred by the bank groups
306 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
307 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
308 # With bank group architectures, tBURST represents the CAS-to-CAS
309 # delay for bursts to different bank groups (tCCD_S)
312 # @2400 data rate, tCCD_L is 6 CK
313 # CAS-to-CAS delay for bursts to the same bank group
314 # tBURST is equivalent to tCCD_S; no explicit parameter required
315 # for CAS-to-CAS delay for bursts to different bank groups
324 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
327 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
336 # Here using the average of WTR_S and WTR_L
339 # Greater of 4 CK or 7.5 ns
342 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
345 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
348 # <=85C, half for >85C
351 # A single DDR3 x64 interface (one command and address bus), with
352 # default timings based on DDR3-1333 4 Gbit parts in an 8x8
353 # configuration, which would amount to 4 GByte of memory. This
354 # configuration is primarily for comparing with DRAMSim2, and all the
355 # parameters except ranks_per_channel are based on the DRAMSim2 config
356 # file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has
357 # to be manually set, depending on size of the memory to be
358 # simulated. By default DRAMSim2 has 2048MB of memory with a single
359 # rank. Therefore for 4 GByte memory, set ranks_per_channel = 2
360 class DDR3_1333_x64_DRAMSim2(DRAMCtrl
):
361 # 8x8 configuration, 8 devices each with an 8-bit interface
364 # DDR3 is a BL8 device
367 # Each device has a page (row buffer) size of 1KB
368 # (this depends on the memory density)
369 device_rowbuffer_size
= '1kB'
371 # 8x8 configuration, so 8 devices
375 ranks_per_channel
= 2
377 # DDR3 has 8 banks in all configurations
390 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz.
391 # Note this is a BL8 DDR device.
396 # DDR3, <=85C, half for >85C
399 # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns
402 # Default same rank rd-to-wr bus turnaround to 2 CK, @666.66 MHz = 3 ns
405 # Default different rank bus delay to 2 CK, @666.66 MHz = 3 ns
414 # A single LPDDR2-S4 x32 interface (one command/address bus), with
415 # default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
417 class LPDDR2_S4_1066_x32(DRAMCtrl
):
418 # 1x32 configuration, 1 device with a 32-bit interface
419 device_bus_width
= 32
421 # LPDDR2_S4 is a BL4 and BL8 device
424 # Each device has a page (row buffer) size of 1KB
425 # (this depends on the memory density)
426 device_rowbuffer_size
= '1kB'
428 # 1x32 configuration, so 1 device
432 ranks_per_channel
= 1
434 # LPDDR2-S4 has 8 banks in all configurations
443 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
446 # Pre-charge one bank 15 ns (all banks 18 ns)
452 # 6 CK read to precharge delay
455 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
456 # Note this is a BL8 DDR device.
457 # Requests larger than 32 bytes are broken down into multiple requests
465 # Irrespective of speed grade, tWTR is 7.5 ns
468 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
471 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
474 # Activate to activate irrespective of density and speed grade
477 # Irrespective of density, tFAW is 50 ns
481 # A single WideIO x128 interface (one command and address bus), with
482 # default timings based on an estimated WIO-200 8 Gbit part.
483 class WideIO_200_x128(DRAMCtrl
):
484 # 1x128 configuration, 1 device with a 128-bit interface
485 device_bus_width
= 128
487 # This is a BL4 device
490 # Each device has a page (row buffer) size of 4KB
491 # (this depends on the memory density)
492 device_rowbuffer_size
= '4kB'
494 # 1x128 configuration, so 1 device
497 # Use one rank for a one-high die stack
498 ranks_per_channel
= 1
500 # WideIO has 4 banks in all configurations
512 # Read to precharge is same as the burst
515 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
516 # Note this is a BL4 SDR device.
522 # WIO 8 Gb, <=85C, half for >85C
525 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
528 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
531 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
534 # Activate to activate irrespective of density and speed grade
537 # Two instead of four activation window
541 # A single LPDDR3 x32 interface (one command/address bus), with
542 # default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
544 class LPDDR3_1600_x32(DRAMCtrl
):
545 # 1x32 configuration, 1 device with a 32-bit interface
546 device_bus_width
= 32
548 # LPDDR3 is a BL8 device
551 # Each device has a page (row buffer) size of 4KB
552 device_rowbuffer_size
= '4kB'
554 # 1x32 configuration, so 1 device
558 ranks_per_channel
= 1
560 # LPDDR3 has 8 banks in all configurations
569 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
575 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
578 # Pre-charge one bank 15 ns (all banks 18 ns)
581 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
582 # Note this is a BL8 DDR device.
583 # Requests larger than 32 bytes are broken down into multiple requests
591 # Irrespective of speed grade, tWTR is 7.5 ns
594 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
597 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
600 # Activate to activate irrespective of density and speed grade
603 # Irrespective of size, tFAW is 50 ns