1 # Copyright (c) 2012-2018 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2013 Amin Farmahini-Farahani
14 # Copyright (c) 2015 University of Kaiserslautern
15 # Copyright (c) 2015 The University of Bologna
16 # All rights reserved.
18 # Redistribution and use in source and binary forms, with or without
19 # modification, are permitted provided that the following conditions are
20 # met: redistributions of source code must retain the above copyright
21 # notice, this list of conditions and the following disclaimer;
22 # redistributions in binary form must reproduce the above copyright
23 # notice, this list of conditions and the following disclaimer in the
24 # documentation and/or other materials provided with the distribution;
25 # neither the name of the copyright holders nor the names of its
26 # contributors may be used to endorse or promote products derived from
27 # this software without specific prior written permission.
29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 # Authors: Andreas Hansson
47 from m5
.params
import *
48 from m5
.proxy
import *
49 from m5
.objects
.AbstractMemory
import *
50 from m5
.objects
.QoSMemCtrl
import *
52 # Enum for memory scheduling algorithms, currently First-Come
53 # First-Served and a First-Row Hit then First-Come First-Served
54 class MemSched(Enum
): vals
= ['fcfs', 'frfcfs']
56 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
57 # channel, rank, bank, row and column, respectively, and going from
58 # MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
59 # suitable for an open-page policy, optimising for sequential accesses
60 # hitting in the open row. For a closed-page policy, RoCoRaBaCh
61 # maximises parallelism.
62 class AddrMap(Enum
): vals
= ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
64 # Enum for the page policy, either open, open_adaptive, close, or
66 class PageManage(Enum
): vals
= ['open', 'open_adaptive', 'close',
69 # DRAMCtrl is a single-channel single-ported DRAM controller model
70 # that aims to model the most important system-level performance
71 # effects of a DRAM without getting into too much detail of the DRAM
73 class DRAMCtrl(QoSMemCtrl
):
75 cxx_header
= "mem/dram_ctrl.hh"
77 # single-ported on the system interface side, instantiate with a
78 # bus in front of the controller for multiple ports
79 port
= SlavePort("Slave port")
81 # the basic configuration of the controller architecture, note
82 # that each entry corresponds to a burst for the specific DRAM
83 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
84 # the cacheline size or request/packet size
85 write_buffer_size
= Param
.Unsigned(64, "Number of write queue entries")
86 read_buffer_size
= Param
.Unsigned(32, "Number of read queue entries")
88 # threshold in percent for when to forcefully trigger writes and
89 # start emptying the write buffer
90 write_high_thresh_perc
= Param
.Percent(85, "Threshold to force writes")
92 # threshold in percentage for when to start writes if the read
94 write_low_thresh_perc
= Param
.Percent(50, "Threshold to start writes")
96 # minimum write bursts to schedule before switching back to reads
97 min_writes_per_switch
= Param
.Unsigned(16, "Minimum write bursts before "
100 # scheduler, address map and page policy
101 mem_sched_policy
= Param
.MemSched('frfcfs', "Memory scheduling policy")
102 addr_mapping
= Param
.AddrMap('RoRaBaCoCh', "Address mapping policy")
103 page_policy
= Param
.PageManage('open_adaptive', "Page management policy")
105 # enforce a limit on the number of accesses per row
106 max_accesses_per_row
= Param
.Unsigned(16, "Max accesses per row before "
109 # size of DRAM Chip in Bytes
110 device_size
= Param
.MemorySize("Size of DRAM chip")
112 # pipeline latency of the controller and PHY, split into a
113 # frontend part and a backend part, with reads and writes serviced
114 # by the queues only seeing the frontend contribution, and reads
115 # serviced by the memory seeing the sum of the two
116 static_frontend_latency
= Param
.Latency("10ns", "Static frontend latency")
117 static_backend_latency
= Param
.Latency("10ns", "Static backend latency")
119 # the physical organisation of the DRAM
120 device_bus_width
= Param
.Unsigned("data bus width in bits for each DRAM "\
122 burst_length
= Param
.Unsigned("Burst lenght (BL) in beats")
123 device_rowbuffer_size
= Param
.MemorySize("Page (row buffer) size per "\
125 devices_per_rank
= Param
.Unsigned("Number of devices/chips per rank")
126 ranks_per_channel
= Param
.Unsigned("Number of ranks per channel")
128 # default to 0 bank groups per rank, indicating bank group architecture
130 # update per memory class when bank group architecture is supported
131 bank_groups_per_rank
= Param
.Unsigned(0, "Number of bank groups per rank")
132 banks_per_rank
= Param
.Unsigned("Number of banks per rank")
133 # only used for the address mapping as the controller by
134 # construction is a single channel and multiple controllers have
135 # to be instantiated for a multi-channel configuration
136 channels
= Param
.Unsigned(1, "Number of channels")
138 # Enable DRAM powerdown states if True. This is False by default due to
139 # performance being lower when enabled
140 enable_dram_powerdown
= Param
.Bool(False, "Enable powerdown states")
142 # For power modelling we need to know if the DRAM has a DLL or not
143 dll
= Param
.Bool(True, "DRAM has DLL or not")
145 # DRAMPower provides in addition to the core power, the possibility to
146 # include RD/WR termination and IO power. This calculation assumes some
147 # default values. The integration of DRAMPower with gem5 does not include
148 # IO and RD/WR termination power by default. This might be added as an
149 # additional feature in the future.
151 # timing behaviour and constraints - all in nanoseconds
153 # the base clock period of the DRAM
154 tCK
= Param
.Latency("Clock period")
156 # the amount of time in nanoseconds from issuing an activate command
157 # to the data being available in the row buffer for a read/write
158 tRCD
= Param
.Latency("RAS to CAS delay")
160 # the time from issuing a read/write command to seeing the actual data
161 tCL
= Param
.Latency("CAS latency")
163 # minimum time between a precharge and subsequent activate
164 tRP
= Param
.Latency("Row precharge time")
166 # minimum time between an activate and a precharge to the same row
167 tRAS
= Param
.Latency("ACT to PRE delay")
169 # minimum time between a write data transfer and a precharge
170 tWR
= Param
.Latency("Write recovery time")
172 # minimum time between a read and precharge command
173 tRTP
= Param
.Latency("Read to precharge")
175 # time to complete a burst transfer, typically the burst length
176 # divided by two due to the DDR bus, but by making it a parameter
177 # it is easier to also evaluate SDR memories like WideIO.
178 # This parameter has to account for burst length.
179 # Read/Write requests with data size larger than one full burst are broken
180 # down into multiple requests in the controller
181 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
182 # With bank group architectures, tBURST represents the CAS-to-CAS
183 # delay for bursts to different bank groups (tCCD_S)
184 tBURST
= Param
.Latency("Burst duration (for DDR burst length / 2 cycles)")
186 # CAS-to-CAS delay for bursts to the same bank group
187 # only utilized with bank group architectures; set to 0 for default case
188 # tBURST is equivalent to tCCD_S; no explicit parameter required
189 # for CAS-to-CAS delay for bursts to different bank groups
190 tCCD_L
= Param
.Latency("0ns", "Same bank group CAS to CAS delay")
192 # Write-to-Write delay for bursts to the same bank group
193 # only utilized with bank group architectures; set to 0 for default case
194 # This will be used to enable different same bank group delays
195 # for writes versus reads
196 tCCD_L_WR
= Param
.Latency(Self
.tCCD_L
,
197 "Same bank group Write to Write delay")
199 # time taken to complete one refresh cycle (N rows in all banks)
200 tRFC
= Param
.Latency("Refresh cycle time")
202 # refresh command interval, how often a "ref" command needs
203 # to be sent. It is 7.8 us for a 64ms refresh requirement
204 tREFI
= Param
.Latency("Refresh command interval")
206 # write-to-read, same rank turnaround penalty
207 tWTR
= Param
.Latency("Write to read, same rank switching time")
209 # read-to-write, same rank turnaround penalty
210 tRTW
= Param
.Latency("Read to write, same rank switching time")
212 # rank-to-rank bus delay penalty
213 # this does not correlate to a memory timing parameter and encompasses:
214 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
215 # different rank bus delay
216 tCS
= Param
.Latency("Rank to rank switching time")
218 # minimum row activate to row activate delay time
219 tRRD
= Param
.Latency("ACT to ACT delay")
221 # only utilized with bank group architectures; set to 0 for default case
222 tRRD_L
= Param
.Latency("0ns", "Same bank group ACT to ACT delay")
224 # time window in which a maximum number of activates are allowed
225 # to take place, set to 0 to disable
226 tXAW
= Param
.Latency("X activation window")
227 activation_limit
= Param
.Unsigned("Max number of activates in window")
229 # time to exit power-down mode
230 # Exit power-down to next valid command delay
231 tXP
= Param
.Latency("0ns", "Power-up Delay")
233 # Exit Powerdown to commands requiring a locked DLL
234 tXPDLL
= Param
.Latency("0ns", "Power-up Delay with locked DLL")
236 # time to exit self-refresh mode
237 tXS
= Param
.Latency("0ns", "Self-refresh exit latency")
239 # time to exit self-refresh mode with locked DLL
240 tXSDLL
= Param
.Latency("0ns", "Self-refresh exit latency DLL")
242 # Currently rolled into other params
243 ######################################################################
245 # tRC - assumed to be tRAS + tRP
247 # Power Behaviour and Constraints
248 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
249 # defined as VDD and VDD2. Each current is defined for each voltage domain
250 # separately. For example, current IDD0 is active-precharge current for
251 # voltage domain VDD and current IDD02 is active-precharge current for
252 # voltage domain VDD2.
253 # By default all currents are set to 0mA. Users who are only interested in
254 # the performance of DRAMs can leave them at 0.
256 # Operating 1 Bank Active-Precharge current
257 IDD0
= Param
.Current("0mA", "Active precharge current")
259 # Operating 1 Bank Active-Precharge current multiple voltage Range
260 IDD02
= Param
.Current("0mA", "Active precharge current VDD2")
262 # Precharge Power-down Current: Slow exit
263 IDD2P0
= Param
.Current("0mA", "Precharge Powerdown slow")
265 # Precharge Power-down Current: Slow exit multiple voltage Range
266 IDD2P02
= Param
.Current("0mA", "Precharge Powerdown slow VDD2")
268 # Precharge Power-down Current: Fast exit
269 IDD2P1
= Param
.Current("0mA", "Precharge Powerdown fast")
271 # Precharge Power-down Current: Fast exit multiple voltage Range
272 IDD2P12
= Param
.Current("0mA", "Precharge Powerdown fast VDD2")
274 # Precharge Standby current
275 IDD2N
= Param
.Current("0mA", "Precharge Standby current")
277 # Precharge Standby current multiple voltage range
278 IDD2N2
= Param
.Current("0mA", "Precharge Standby current VDD2")
280 # Active Power-down current: slow exit
281 IDD3P0
= Param
.Current("0mA", "Active Powerdown slow")
283 # Active Power-down current: slow exit multiple voltage range
284 IDD3P02
= Param
.Current("0mA", "Active Powerdown slow VDD2")
286 # Active Power-down current : fast exit
287 IDD3P1
= Param
.Current("0mA", "Active Powerdown fast")
289 # Active Power-down current : fast exit multiple voltage range
290 IDD3P12
= Param
.Current("0mA", "Active Powerdown fast VDD2")
292 # Active Standby current
293 IDD3N
= Param
.Current("0mA", "Active Standby current")
295 # Active Standby current multiple voltage range
296 IDD3N2
= Param
.Current("0mA", "Active Standby current VDD2")
298 # Burst Read Operating Current
299 IDD4R
= Param
.Current("0mA", "READ current")
301 # Burst Read Operating Current multiple voltage range
302 IDD4R2
= Param
.Current("0mA", "READ current VDD2")
304 # Burst Write Operating Current
305 IDD4W
= Param
.Current("0mA", "WRITE current")
307 # Burst Write Operating Current multiple voltage range
308 IDD4W2
= Param
.Current("0mA", "WRITE current VDD2")
311 IDD5
= Param
.Current("0mA", "Refresh current")
313 # Refresh Current multiple voltage range
314 IDD52
= Param
.Current("0mA", "Refresh current VDD2")
316 # Self-Refresh Current
317 IDD6
= Param
.Current("0mA", "Self-refresh Current")
319 # Self-Refresh Current multiple voltage range
320 IDD62
= Param
.Current("0mA", "Self-refresh Current VDD2")
322 # Main voltage range of the DRAM
323 VDD
= Param
.Voltage("0V", "Main Voltage Range")
325 # Second voltage range defined by some DRAMs
326 VDD2
= Param
.Voltage("0V", "2nd Voltage Range")
328 # A single DDR3-1600 x64 channel (one command and address bus), with
329 # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
330 # an 8x8 configuration.
331 class DDR3_1600_8x8(DRAMCtrl
):
332 # size of device in bytes
333 device_size
= '512MB'
335 # 8x8 configuration, 8 devices each with an 8-bit interface
338 # DDR3 is a BL8 device
341 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
342 device_rowbuffer_size
= '1kB'
344 # 8x8 configuration, so 8 devices
348 ranks_per_channel
= 2
350 # DDR3 has 8 banks in all configurations
356 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
371 # Greater of 4 CK or 7.5 ns
374 # Greater of 4 CK or 7.5 ns
377 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
380 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
383 # <=85C, half for >85C
386 # active powerdown and precharge powerdown exit time
389 # self refresh exit time
392 # Current values from datasheet Die Rev E,J
404 # A single HMC-2500 x32 model based on:
405 # [1] DRAMSpec: a high-level DRAM bank modelling tool
406 # developed at the University of Kaiserslautern. This high level tool
407 # uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
408 # estimate the DRAM bank latency and power numbers.
409 # [2] High performance AXI-4.0 based interconnect for extensible smart memory
410 # cubes (E. Azarkhish et. al)
411 # Assumed for the HMC model is a 30 nm technology node.
412 # The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
414 # Each layer has 16 vaults and each vault consists of 2 banks per layer.
415 # In order to be able to use the same controller used for 2D DRAM generations
416 # for HMC, the following analogy is done:
417 # Channel (DDR) => Vault (HMC)
418 # device_size (DDR) => size of a single layer in a vault
419 # ranks per channel (DDR) => number of layers
420 # banks per rank (DDR) => banks per layer
421 # devices per rank (DDR) => devices per layer ( 1 for HMC).
422 # The parameters for which no input is available are inherited from the DDR3
424 # This configuration includes the latencies from the DRAM to the logic layer
426 class HMC_2500_1x32(DDR3_1600_8x8
):
428 # two banks per device with each bank 4MB [2]
431 # 1x32 configuration, 1 device with 32 TSVs [2]
432 device_bus_width
= 32
434 # HMC is a BL8 device [2]
437 # Each device has a page (row buffer) size of 256 bytes [2]
438 device_rowbuffer_size
= '256B'
440 # 1x32 configuration, so 1 device [2]
443 # 4 layers so 4 ranks [2]
444 ranks_per_channel
= 4
446 # HMC has 2 banks per layer [2]
447 # Each layer represents a rank. With 4 layers and 8 banks in total, each
448 # layer has 2 banks; thus 2 banks per rank.
454 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
457 # Values using DRAMSpec HMC model [1]
463 # tRRD depends on the power supply network for each vendor.
464 # We assume a tRRD of a double bank approach to be equal to 4 clock
465 # cycles (Assumption)
468 # activation limit is set to 0 since there are only 2 banks per vault
472 # Values using DRAMSpec HMC model [1]
477 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
478 # 0.8 ns (Assumption)
481 # Value using DRAMSpec HMC model [1]
484 # The default page policy in the vault controllers is simple closed page
485 # [2] nevertheless 'close' policy opens and closes the row multiple times
486 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
487 page_policy
= 'close_adaptive'
489 # RoCoRaBaCh resembles the default address mapping in HMC
490 addr_mapping
= 'RoCoRaBaCh'
491 min_writes_per_switch
= 8
493 # These parameters do not directly correlate with buffer_size in real
494 # hardware. Nevertheless, their value has been tuned to achieve a
495 # bandwidth similar to the cycle-accurate model in [2]
496 write_buffer_size
= 32
497 read_buffer_size
= 32
499 # The static latency of the vault controllers is estimated to be smaller
500 # than a full DRAM channel controller
501 static_backend_latency
='4ns'
502 static_frontend_latency
='4ns'
504 # A single DDR3-2133 x64 channel refining a selected subset of the
505 # options for the DDR-1600 configuration, based on the same DDR3-1600
506 # 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
507 # consistent across the two configurations.
508 class DDR3_2133_8x8(DDR3_1600_8x8
):
512 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
523 # Current values from datasheet
535 # A single DDR4-2400 x64 channel (one command and address bus), with
536 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
537 # in an 16x4 configuration.
538 # Total channel capacity is 32GB
539 # 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
540 class DDR4_2400_16x4(DRAMCtrl
):
544 # 16x4 configuration, 16 devices each with a 4-bit interface
547 # DDR4 is a BL8 device
550 # Each device has a page (row buffer) size of 512 byte (1K columns x4)
551 device_rowbuffer_size
= '512B'
553 # 16x4 configuration, so 16 devices
554 devices_per_rank
= 16
556 # Match our DDR3 configurations which is dual rank
557 ranks_per_channel
= 2
559 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
560 # Set to 4 for x4 case
561 bank_groups_per_rank
= 4
563 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
564 # configurations). Currently we do not capture the additional
565 # constraints incurred by the bank groups
568 # override the default buffer sizes and go for something larger to
569 # accommodate the larger bank count
570 write_buffer_size
= 128
571 read_buffer_size
= 64
576 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
577 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
578 # With bank group architectures, tBURST represents the CAS-to-CAS
579 # delay for bursts to different bank groups (tCCD_S)
582 # @2400 data rate, tCCD_L is 6 CK
583 # CAS-to-CAS delay for bursts to the same bank group
584 # tBURST is equivalent to tCCD_S; no explicit parameter required
585 # for CAS-to-CAS delay for bursts to different bank groups
594 # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
597 # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
600 # tFAW for 512B page is MAX(16 CK, 13ns)
608 # Here using the average of WTR_S and WTR_L
611 # Greater of 4 CK or 7.5 ns
614 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
617 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
620 # <=85C, half for >85C
623 # active powerdown and precharge powerdown exit time
626 # self refresh exit time
627 # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
628 # tRFC + 10ns = 340ns
631 # Current values from datasheet
646 # A single DDR4-2400 x64 channel (one command and address bus), with
647 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
648 # in an 8x8 configuration.
649 # Total channel capacity is 16GB
650 # 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
651 class DDR4_2400_8x8(DDR4_2400_16x4
):
652 # 8x8 configuration, 8 devices each with an 8-bit interface
655 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
656 device_rowbuffer_size
= '1kB'
658 # 8x8 configuration, so 8 devices
661 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
666 # Current values from datasheet
673 # A single DDR4-2400 x64 channel (one command and address bus), with
674 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
675 # in an 4x16 configuration.
676 # Total channel capacity is 4GB
677 # 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
678 class DDR4_2400_4x16(DDR4_2400_16x4
):
679 # 4x16 configuration, 4 devices each with an 16-bit interface
680 device_bus_width
= 16
682 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
683 device_rowbuffer_size
= '2kB'
685 # 4x16 configuration, so 4 devices
688 # Single rank for x16
689 ranks_per_channel
= 1
691 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
692 # Set to 2 for x16 case
693 bank_groups_per_rank
= 2
695 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
696 # configurations). Currently we do not capture the additional
697 # constraints incurred by the bank groups
700 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
703 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
708 # Current values from datasheet
718 # A single LPDDR2-S4 x32 interface (one command/address bus), with
719 # default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
720 # in a 1x32 configuration.
721 class LPDDR2_S4_1066_1x32(DRAMCtrl
):
726 device_size
= '512MB'
728 # 1x32 configuration, 1 device with a 32-bit interface
729 device_bus_width
= 32
731 # LPDDR2_S4 is a BL4 and BL8 device
734 # Each device has a page (row buffer) size of 1KB
735 # (this depends on the memory density)
736 device_rowbuffer_size
= '1kB'
738 # 1x32 configuration, so 1 device
742 ranks_per_channel
= 1
744 # LPDDR2-S4 has 8 banks in all configurations
753 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
756 # Pre-charge one bank 15 ns (all banks 18 ns)
764 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
765 # Note this is a BL8 DDR device.
766 # Requests larger than 32 bytes are broken down into multiple requests
774 # active powerdown and precharge powerdown exit time
777 # self refresh exit time
780 # Irrespective of speed grade, tWTR is 7.5 ns
783 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
786 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
789 # Activate to activate irrespective of density and speed grade
792 # Irrespective of density, tFAW is 50 ns
796 # Current values from datasheet
818 # A single WideIO x128 interface (one command and address bus), with
819 # default timings based on an estimated WIO-200 8 Gbit part.
820 class WideIO_200_1x128(DRAMCtrl
):
825 device_size
= '1024MB'
827 # 1x128 configuration, 1 device with a 128-bit interface
828 device_bus_width
= 128
830 # This is a BL4 device
833 # Each device has a page (row buffer) size of 4KB
834 # (this depends on the memory density)
835 device_rowbuffer_size
= '4kB'
837 # 1x128 configuration, so 1 device
840 # Use one rank for a one-high die stack
841 ranks_per_channel
= 1
843 # WideIO has 4 banks in all configurations
855 # Read to precharge is same as the burst
858 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
859 # Note this is a BL4 SDR device.
865 # WIO 8 Gb, <=85C, half for >85C
868 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
871 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
874 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
877 # Activate to activate irrespective of density and speed grade
880 # Two instead of four activation window
884 # The WideIO specification does not provide current information
886 # A single LPDDR3 x32 interface (one command/address bus), with
887 # default timings based on a LPDDR3-1600 4 Gbit part (Micron
888 # EDF8132A1MC) in a 1x32 configuration.
889 class LPDDR3_1600_1x32(DRAMCtrl
):
894 device_size
= '512MB'
896 # 1x32 configuration, 1 device with a 32-bit interface
897 device_bus_width
= 32
899 # LPDDR3 is a BL8 device
902 # Each device has a page (row buffer) size of 4KB
903 device_rowbuffer_size
= '4kB'
905 # 1x32 configuration, so 1 device
908 # Technically the datasheet is a dual-rank package, but for
909 # comparison with the LPDDR2 config we stick to a single rank
910 ranks_per_channel
= 1
912 # LPDDR3 has 8 banks in all configurations
920 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
926 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
929 # Pre-charge one bank 18 ns (all banks 21 ns)
932 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
933 # Note this is a BL8 DDR device.
934 # Requests larger than 32 bytes are broken down into multiple requests
942 # active powerdown and precharge powerdown exit time
945 # self refresh exit time
948 # Irrespective of speed grade, tWTR is 7.5 ns
951 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
954 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
957 # Activate to activate irrespective of density and speed grade
960 # Irrespective of size, tFAW is 50 ns
964 # Current values from datasheet
986 # A single GDDR5 x64 interface, with
987 # default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
988 # H5GQ1H24AFR) in a 2x32 configuration.
989 class GDDR5_4000_2x32(DRAMCtrl
):
991 device_size
= '128MB'
993 # 2x32 configuration, 1 device with a 32-bit interface
994 device_bus_width
= 32
996 # GDDR5 is a BL8 device
999 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
1000 device_rowbuffer_size
= '256B'
1002 # 2x32 configuration, so 2 devices
1003 devices_per_rank
= 2
1005 # assume single rank
1006 ranks_per_channel
= 1
1008 # GDDR5 has 4 bank groups
1009 bank_groups_per_rank
= 4
1011 # GDDR5 has 16 banks with 4 bank groups
1017 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
1018 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
1019 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
1020 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
1021 # With bank group architectures, tBURST represents the CAS-to-CAS
1022 # delay for bursts to different bank groups (tCCD_S)
1025 # @1000MHz data rate, tCCD_L is 3 CK
1026 # CAS-to-CAS delay for bursts to the same bank group
1027 # tBURST is equivalent to tCCD_S; no explicit parameter required
1028 # for CAS-to-CAS delay for bursts to different bank groups
1033 # tCL is not directly found in datasheet and assumed equal tRCD
1039 # RRD_S (different bank group)
1040 # RRD_S is 5.5 ns in datasheet.
1041 # rounded to the next multiple of tCK
1044 # RRD_L (same bank group)
1045 # RRD_L is 5.5 ns in datasheet.
1046 # rounded to the next multiple of tCK
1052 # Therefore, activation limit is set to 0
1053 activation_limit
= 0
1058 # Here using the average of WTR_S and WTR_L
1061 # Read-to-Precharge 2 CK
1067 # A single HBM x128 interface (one command and address bus), with
1068 # default timings based on data publically released
1069 # ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
1070 # IDD measurement values, and by extrapolating data from other classes.
1071 # Architecture values based on published HBM spec
1072 # A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
1073 class HBM_1000_4H_1x128(DRAMCtrl
):
1074 # HBM gen1 supports up to 8 128-bit physical channels
1075 # Configuration defines a single channel, with the capacity
1076 # set to (full_ stack_capacity / 8) based on 2Gb dies
1077 # To use all 8 channels, set 'channels' parameter to 8 in
1078 # system configuration
1080 # 128-bit interface legacy mode
1081 device_bus_width
= 128
1083 # HBM supports BL4 and BL2 (legacy mode only)
1086 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
1087 # with 8 channels, 128MB per channel
1088 device_size
= '128MB'
1090 device_rowbuffer_size
= '2kB'
1092 # 1x128 configuration
1093 devices_per_rank
= 1
1095 # HBM does not have a CS pin; set rank to 1
1096 ranks_per_channel
= 1
1098 # HBM has 8 or 16 banks depending on capacity
1099 # 2Gb dies have 8 banks
1102 # depending on frequency, bank groups may be required
1103 # will always have 4 bank groups when enabled
1104 # current specifications do not define the minimum frequency for
1105 # bank group architecture
1106 # setting bank_groups_per_rank to 0 to disable until range is defined
1107 bank_groups_per_rank
= 0
1109 # 500 MHz for 1Gbps DDR data rate
1112 # use values from IDD measurement in JEDEC spec
1113 # use tRP value for tRCD and tCL similar to other classes
1119 # BL2 and BL4 supported, default to BL4
1120 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
1123 # value for 2Gb device from JEDEC spec
1126 # value for 2Gb device from JEDEC spec
1129 # extrapolate the following from LPDDR configs, using ns values
1130 # to minimize burst length, prefetch differences
1135 # start with 2 cycles turnaround, similar to other memory classes
1136 # could be more with variations across the stack
1139 # single rank device, set to 0
1142 # from MemCon example, tRRD is 4ns with 2ns tCK
1145 # from MemCon example, tFAW is 30ns with 2ns tCK
1147 activation_limit
= 4
1152 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1155 # A single HBM x64 interface (one command and address bus), with
1156 # default timings based on HBM gen1 and data publically released
1157 # A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1158 # Note: This defines a pseudo-channel with a unique controller
1159 # instantiated per pseudo-channel
1160 # Stay at same IO rate (1Gbps) to maintain timing relationship with
1161 # HBM gen1 class (HBM_1000_4H_x128) where possible
1162 class HBM_1000_4H_1x64(HBM_1000_4H_1x128
):
1163 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1164 # Configuration defines a single pseudo channel, with the capacity
1165 # set to (full_ stack_capacity / 16) based on 8Gb dies
1166 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1167 # system configuration
1169 # 64-bit pseudo-channle interface
1170 device_bus_width
= 64
1172 # HBM pseudo-channel only supports BL4
1175 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1176 # with 16 channels, 256MB per channel
1177 device_size
= '256MB'
1179 # page size is halved with pseudo-channel; maintaining the same same number
1180 # of rows per pseudo-channel with 2X banks across 2 channels
1181 device_rowbuffer_size
= '1kB'
1183 # HBM has 8 or 16 banks depending on capacity
1184 # Starting with 4Gb dies, 16 banks are defined
1187 # reset tRFC for larger, 8Gb device
1188 # use HBM1 4Gb value as a starting point
1191 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1193 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1197 # active powerdown and precharge powerdown exit time
1200 # self refresh exit time