1 # Copyright (c) 2012-2020 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2013 Amin Farmahini-Farahani
14 # Copyright (c) 2015 University of Kaiserslautern
15 # Copyright (c) 2015 The University of Bologna
16 # All rights reserved.
18 # Redistribution and use in source and binary forms, with or without
19 # modification, are permitted provided that the following conditions are
20 # met: redistributions of source code must retain the above copyright
21 # notice, this list of conditions and the following disclaimer;
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41 from m5
.objects
.MemInterface
import *
43 # Enum for the page policy, either open, open_adaptive, close, or
45 class PageManage(Enum
): vals
= ['open', 'open_adaptive', 'close',
48 class DRAMInterface(MemInterface
):
49 type = 'DRAMInterface'
50 cxx_header
= "mem/mem_interface.hh"
52 # scheduler page policy
53 page_policy
= Param
.PageManage('open_adaptive', "Page management policy")
55 # enforce a limit on the number of accesses per row
56 max_accesses_per_row
= Param
.Unsigned(16, "Max accesses per row before "
59 # default to 0 bank groups per rank, indicating bank group architecture
61 # update per memory class when bank group architecture is supported
62 bank_groups_per_rank
= Param
.Unsigned(0, "Number of bank groups per rank")
64 # Enable DRAM powerdown states if True. This is False by default due to
65 # performance being lower when enabled
66 enable_dram_powerdown
= Param
.Bool(False, "Enable powerdown states")
68 # For power modelling we need to know if the DRAM has a DLL or not
69 dll
= Param
.Bool(True, "DRAM has DLL or not")
71 # DRAMPower provides in addition to the core power, the possibility to
72 # include RD/WR termination and IO power. This calculation assumes some
73 # default values. The integration of DRAMPower with gem5 does not include
74 # IO and RD/WR termination power by default. This might be added as an
75 # additional feature in the future.
77 # timing behaviour and constraints - all in nanoseconds
79 # the amount of time in nanoseconds from issuing an activate command
80 # to the data being available in the row buffer for a read/write
81 tRCD
= Param
.Latency("RAS to CAS delay")
83 # the time from issuing a read/write command to seeing the actual data
84 tCL
= Param
.Latency("CAS latency")
86 # minimum time between a precharge and subsequent activate
87 tRP
= Param
.Latency("Row precharge time")
89 # minimum time between an activate and a precharge to the same row
90 tRAS
= Param
.Latency("ACT to PRE delay")
92 # minimum time between a write data transfer and a precharge
93 tWR
= Param
.Latency("Write recovery time")
95 # minimum time between a read and precharge command
96 tRTP
= Param
.Latency("Read to precharge")
98 # tBURST_MAX is the column array cycle delay required before next access,
99 # which could be greater than tBURST when the memory access time is greater
101 tBURST_MAX
= Param
.Latency(Self
.tBURST
, "Column access delay")
103 # tBURST_MIN is the minimum delay between bursts, which could be less than
104 # tBURST when interleaving is supported
105 tBURST_MIN
= Param
.Latency(Self
.tBURST
, "Minimim delay between bursts")
107 # CAS-to-CAS delay for bursts to the same bank group
108 # only utilized with bank group architectures; set to 0 for default case
109 # tBURST is equivalent to tCCD_S; no explicit parameter required
110 # for CAS-to-CAS delay for bursts to different bank groups
111 tCCD_L
= Param
.Latency("0ns", "Same bank group CAS to CAS delay")
113 # Write-to-Write delay for bursts to the same bank group
114 # only utilized with bank group architectures; set to 0 for default case
115 # This will be used to enable different same bank group delays
116 # for writes versus reads
117 tCCD_L_WR
= Param
.Latency(Self
.tCCD_L
,
118 "Same bank group Write to Write delay")
120 # time taken to complete one refresh cycle (N rows in all banks)
121 tRFC
= Param
.Latency("Refresh cycle time")
123 # refresh command interval, how often a "ref" command needs
124 # to be sent. It is 7.8 us for a 64ms refresh requirement
125 tREFI
= Param
.Latency("Refresh command interval")
127 # write-to-read, same rank turnaround penalty for same bank group
128 tWTR_L
= Param
.Latency(Self
.tWTR
, "Write to read, same rank switching "
129 "time, same bank group")
131 # minimum precharge to precharge delay time
132 tPPD
= Param
.Latency("0ns", "PRE to PRE delay")
134 # maximum delay between two-cycle ACT command phases
135 tAAD
= Param
.Latency(Self
.tCK
,
136 "Maximum delay between two-cycle ACT commands")
138 two_cycle_activate
= Param
.Bool(False,
139 "Two cycles required to send activate")
141 # minimum row activate to row activate delay time
142 tRRD
= Param
.Latency("ACT to ACT delay")
144 # only utilized with bank group architectures; set to 0 for default case
145 tRRD_L
= Param
.Latency("0ns", "Same bank group ACT to ACT delay")
147 # time window in which a maximum number of activates are allowed
148 # to take place, set to 0 to disable
149 tXAW
= Param
.Latency("X activation window")
150 activation_limit
= Param
.Unsigned("Max number of activates in window")
152 # time to exit power-down mode
153 # Exit power-down to next valid command delay
154 tXP
= Param
.Latency("0ns", "Power-up Delay")
156 # Exit Powerdown to commands requiring a locked DLL
157 tXPDLL
= Param
.Latency("0ns", "Power-up Delay with locked DLL")
159 # time to exit self-refresh mode
160 tXS
= Param
.Latency("0ns", "Self-refresh exit latency")
162 # time to exit self-refresh mode with locked DLL
163 tXSDLL
= Param
.Latency("0ns", "Self-refresh exit latency DLL")
165 # number of data beats per clock. with DDR, default is 2, one per edge
166 # used in drampower.cc
167 beats_per_clock
= Param
.Unsigned(2, "Data beats per clock")
169 data_clock_sync
= Param
.Bool(False, "Synchronization commands required")
171 # Currently rolled into other params
172 ######################################################################
174 # tRC - assumed to be tRAS + tRP
176 # Power Behaviour and Constraints
177 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
178 # defined as VDD and VDD2. Each current is defined for each voltage domain
179 # separately. For example, current IDD0 is active-precharge current for
180 # voltage domain VDD and current IDD02 is active-precharge current for
181 # voltage domain VDD2.
182 # By default all currents are set to 0mA. Users who are only interested in
183 # the performance of DRAMs can leave them at 0.
185 # Operating 1 Bank Active-Precharge current
186 IDD0
= Param
.Current("0mA", "Active precharge current")
188 # Operating 1 Bank Active-Precharge current multiple voltage Range
189 IDD02
= Param
.Current("0mA", "Active precharge current VDD2")
191 # Precharge Power-down Current: Slow exit
192 IDD2P0
= Param
.Current("0mA", "Precharge Powerdown slow")
194 # Precharge Power-down Current: Slow exit multiple voltage Range
195 IDD2P02
= Param
.Current("0mA", "Precharge Powerdown slow VDD2")
197 # Precharge Power-down Current: Fast exit
198 IDD2P1
= Param
.Current("0mA", "Precharge Powerdown fast")
200 # Precharge Power-down Current: Fast exit multiple voltage Range
201 IDD2P12
= Param
.Current("0mA", "Precharge Powerdown fast VDD2")
203 # Precharge Standby current
204 IDD2N
= Param
.Current("0mA", "Precharge Standby current")
206 # Precharge Standby current multiple voltage range
207 IDD2N2
= Param
.Current("0mA", "Precharge Standby current VDD2")
209 # Active Power-down current: slow exit
210 IDD3P0
= Param
.Current("0mA", "Active Powerdown slow")
212 # Active Power-down current: slow exit multiple voltage range
213 IDD3P02
= Param
.Current("0mA", "Active Powerdown slow VDD2")
215 # Active Power-down current : fast exit
216 IDD3P1
= Param
.Current("0mA", "Active Powerdown fast")
218 # Active Power-down current : fast exit multiple voltage range
219 IDD3P12
= Param
.Current("0mA", "Active Powerdown fast VDD2")
221 # Active Standby current
222 IDD3N
= Param
.Current("0mA", "Active Standby current")
224 # Active Standby current multiple voltage range
225 IDD3N2
= Param
.Current("0mA", "Active Standby current VDD2")
227 # Burst Read Operating Current
228 IDD4R
= Param
.Current("0mA", "READ current")
230 # Burst Read Operating Current multiple voltage range
231 IDD4R2
= Param
.Current("0mA", "READ current VDD2")
233 # Burst Write Operating Current
234 IDD4W
= Param
.Current("0mA", "WRITE current")
236 # Burst Write Operating Current multiple voltage range
237 IDD4W2
= Param
.Current("0mA", "WRITE current VDD2")
240 IDD5
= Param
.Current("0mA", "Refresh current")
242 # Refresh Current multiple voltage range
243 IDD52
= Param
.Current("0mA", "Refresh current VDD2")
245 # Self-Refresh Current
246 IDD6
= Param
.Current("0mA", "Self-refresh Current")
248 # Self-Refresh Current multiple voltage range
249 IDD62
= Param
.Current("0mA", "Self-refresh Current VDD2")
251 # Main voltage range of the DRAM
252 VDD
= Param
.Voltage("0V", "Main Voltage Range")
254 # Second voltage range defined by some DRAMs
255 VDD2
= Param
.Voltage("0V", "2nd Voltage Range")
257 # A single DDR3-1600 x64 channel (one command and address bus), with
258 # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
259 # an 8x8 configuration.
260 class DDR3_1600_8x8(DRAMInterface
):
261 # size of device in bytes
262 device_size
= '512MB'
264 # 8x8 configuration, 8 devices each with an 8-bit interface
267 # DDR3 is a BL8 device
270 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
271 device_rowbuffer_size
= '1kB'
273 # 8x8 configuration, so 8 devices
277 ranks_per_channel
= 2
279 # DDR3 has 8 banks in all configurations
285 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
300 # Greater of 4 CK or 7.5 ns
303 # Greater of 4 CK or 7.5 ns
306 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
309 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
312 # <=85C, half for >85C
315 # active powerdown and precharge powerdown exit time
318 # self refresh exit time
321 # Current values from datasheet Die Rev E,J
333 # A single HMC-2500 x32 model based on:
334 # [1] DRAMSpec: a high-level DRAM bank modelling tool
335 # developed at the University of Kaiserslautern. This high level tool
336 # uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
337 # estimate the DRAM bank latency and power numbers.
338 # [2] High performance AXI-4.0 based interconnect for extensible smart memory
339 # cubes (E. Azarkhish et. al)
340 # Assumed for the HMC model is a 30 nm technology node.
341 # The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
343 # Each layer has 16 vaults and each vault consists of 2 banks per layer.
344 # In order to be able to use the same controller used for 2D DRAM generations
345 # for HMC, the following analogy is done:
346 # Channel (DDR) => Vault (HMC)
347 # device_size (DDR) => size of a single layer in a vault
348 # ranks per channel (DDR) => number of layers
349 # banks per rank (DDR) => banks per layer
350 # devices per rank (DDR) => devices per layer ( 1 for HMC).
351 # The parameters for which no input is available are inherited from the DDR3
353 # This configuration includes the latencies from the DRAM to the logic layer
355 class HMC_2500_1x32(DDR3_1600_8x8
):
357 # two banks per device with each bank 4MB [2]
360 # 1x32 configuration, 1 device with 32 TSVs [2]
361 device_bus_width
= 32
363 # HMC is a BL8 device [2]
366 # Each device has a page (row buffer) size of 256 bytes [2]
367 device_rowbuffer_size
= '256B'
369 # 1x32 configuration, so 1 device [2]
372 # 4 layers so 4 ranks [2]
373 ranks_per_channel
= 4
375 # HMC has 2 banks per layer [2]
376 # Each layer represents a rank. With 4 layers and 8 banks in total, each
377 # layer has 2 banks; thus 2 banks per rank.
383 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
386 # Values using DRAMSpec HMC model [1]
392 # tRRD depends on the power supply network for each vendor.
393 # We assume a tRRD of a double bank approach to be equal to 4 clock
394 # cycles (Assumption)
397 # activation limit is set to 0 since there are only 2 banks per vault
401 # Values using DRAMSpec HMC model [1]
406 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
407 # 0.8 ns (Assumption)
410 # Value using DRAMSpec HMC model [1]
413 # The default page policy in the vault controllers is simple closed page
414 # [2] nevertheless 'close' policy opens and closes the row multiple times
415 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
416 page_policy
= 'close_adaptive'
418 # RoCoRaBaCh resembles the default address mapping in HMC
419 addr_mapping
= 'RoCoRaBaCh'
421 # These parameters do not directly correlate with buffer_size in real
422 # hardware. Nevertheless, their value has been tuned to achieve a
423 # bandwidth similar to the cycle-accurate model in [2]
424 write_buffer_size
= 32
425 read_buffer_size
= 32
427 # A single DDR3-2133 x64 channel refining a selected subset of the
428 # options for the DDR-1600 configuration, based on the same DDR3-1600
429 # 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
430 # consistent across the two configurations.
431 class DDR3_2133_8x8(DDR3_1600_8x8
):
435 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
446 # Current values from datasheet
458 # A single DDR4-2400 x64 channel (one command and address bus), with
459 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
460 # in an 16x4 configuration.
461 # Total channel capacity is 32GB
462 # 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
463 class DDR4_2400_16x4(DRAMInterface
):
467 # 16x4 configuration, 16 devices each with a 4-bit interface
470 # DDR4 is a BL8 device
473 # Each device has a page (row buffer) size of 512 byte (1K columns x4)
474 device_rowbuffer_size
= '512B'
476 # 16x4 configuration, so 16 devices
477 devices_per_rank
= 16
479 # Match our DDR3 configurations which is dual rank
480 ranks_per_channel
= 2
482 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
483 # Set to 4 for x4 case
484 bank_groups_per_rank
= 4
486 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
487 # configurations). Currently we do not capture the additional
488 # constraints incurred by the bank groups
491 # override the default buffer sizes and go for something larger to
492 # accommodate the larger bank count
493 write_buffer_size
= 128
494 read_buffer_size
= 64
499 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
500 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
501 # With bank group architectures, tBURST represents the CAS-to-CAS
502 # delay for bursts to different bank groups (tCCD_S)
505 # @2400 data rate, tCCD_L is 6 CK
506 # CAS-to-CAS delay for bursts to the same bank group
507 # tBURST is equivalent to tCCD_S; no explicit parameter required
508 # for CAS-to-CAS delay for bursts to different bank groups
517 # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
520 # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
523 # tFAW for 512B page is MAX(16 CK, 13ns)
531 # Here using the average of WTR_S and WTR_L
534 # Greater of 4 CK or 7.5 ns
537 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
540 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
543 # <=85C, half for >85C
546 # active powerdown and precharge powerdown exit time
549 # self refresh exit time
550 # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
551 # tRFC + 10ns = 340ns
554 # Current values from datasheet
569 # A single DDR4-2400 x64 channel (one command and address bus), with
570 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
571 # in an 8x8 configuration.
572 # Total channel capacity is 16GB
573 # 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
574 class DDR4_2400_8x8(DDR4_2400_16x4
):
575 # 8x8 configuration, 8 devices each with an 8-bit interface
578 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
579 device_rowbuffer_size
= '1kB'
581 # 8x8 configuration, so 8 devices
584 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
589 # Current values from datasheet
596 # A single DDR4-2400 x64 channel (one command and address bus), with
597 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
598 # in an 4x16 configuration.
599 # Total channel capacity is 4GB
600 # 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
601 class DDR4_2400_4x16(DDR4_2400_16x4
):
602 # 4x16 configuration, 4 devices each with an 16-bit interface
603 device_bus_width
= 16
605 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
606 device_rowbuffer_size
= '2kB'
608 # 4x16 configuration, so 4 devices
611 # Single rank for x16
612 ranks_per_channel
= 1
614 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
615 # Set to 2 for x16 case
616 bank_groups_per_rank
= 2
618 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
619 # configurations). Currently we do not capture the additional
620 # constraints incurred by the bank groups
623 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
626 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
631 # Current values from datasheet
641 # A single LPDDR2-S4 x32 interface (one command/address bus), with
642 # default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
643 # in a 1x32 configuration.
644 class LPDDR2_S4_1066_1x32(DRAMInterface
):
649 device_size
= '512MB'
651 # 1x32 configuration, 1 device with a 32-bit interface
652 device_bus_width
= 32
654 # LPDDR2_S4 is a BL4 and BL8 device
657 # Each device has a page (row buffer) size of 1KB
658 # (this depends on the memory density)
659 device_rowbuffer_size
= '1kB'
661 # 1x32 configuration, so 1 device
665 ranks_per_channel
= 1
667 # LPDDR2-S4 has 8 banks in all configurations
676 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
679 # Pre-charge one bank 15 ns (all banks 18 ns)
687 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
688 # Note this is a BL8 DDR device.
689 # Requests larger than 32 bytes are broken down into multiple requests
697 # active powerdown and precharge powerdown exit time
700 # self refresh exit time
703 # Irrespective of speed grade, tWTR is 7.5 ns
706 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
709 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
712 # Activate to activate irrespective of density and speed grade
715 # Irrespective of density, tFAW is 50 ns
719 # Current values from datasheet
741 # A single WideIO x128 interface (one command and address bus), with
742 # default timings based on an estimated WIO-200 8 Gbit part.
743 class WideIO_200_1x128(DRAMInterface
):
748 device_size
= '1024MB'
750 # 1x128 configuration, 1 device with a 128-bit interface
751 device_bus_width
= 128
753 # This is a BL4 device
756 # Each device has a page (row buffer) size of 4KB
757 # (this depends on the memory density)
758 device_rowbuffer_size
= '4kB'
760 # 1x128 configuration, so 1 device
763 # Use one rank for a one-high die stack
764 ranks_per_channel
= 1
766 # WideIO has 4 banks in all configurations
778 # Read to precharge is same as the burst
781 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
782 # Note this is a BL4 SDR device.
788 # WIO 8 Gb, <=85C, half for >85C
791 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
794 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
797 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
800 # Activate to activate irrespective of density and speed grade
803 # Two instead of four activation window
807 # The WideIO specification does not provide current information
809 # A single LPDDR3 x32 interface (one command/address bus), with
810 # default timings based on a LPDDR3-1600 4 Gbit part (Micron
811 # EDF8132A1MC) in a 1x32 configuration.
812 class LPDDR3_1600_1x32(DRAMInterface
):
817 device_size
= '512MB'
819 # 1x32 configuration, 1 device with a 32-bit interface
820 device_bus_width
= 32
822 # LPDDR3 is a BL8 device
825 # Each device has a page (row buffer) size of 4KB
826 device_rowbuffer_size
= '4kB'
828 # 1x32 configuration, so 1 device
831 # Technically the datasheet is a dual-rank package, but for
832 # comparison with the LPDDR2 config we stick to a single rank
833 ranks_per_channel
= 1
835 # LPDDR3 has 8 banks in all configurations
843 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
849 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
852 # Pre-charge one bank 18 ns (all banks 21 ns)
855 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
856 # Note this is a BL8 DDR device.
857 # Requests larger than 32 bytes are broken down into multiple requests
865 # active powerdown and precharge powerdown exit time
868 # self refresh exit time
871 # Irrespective of speed grade, tWTR is 7.5 ns
874 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
877 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
880 # Activate to activate irrespective of density and speed grade
883 # Irrespective of size, tFAW is 50 ns
887 # Current values from datasheet
909 # A single GDDR5 x64 interface, with
910 # default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
911 # H5GQ1H24AFR) in a 2x32 configuration.
912 class GDDR5_4000_2x32(DRAMInterface
):
914 device_size
= '128MB'
916 # 2x32 configuration, 1 device with a 32-bit interface
917 device_bus_width
= 32
919 # GDDR5 is a BL8 device
922 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
923 device_rowbuffer_size
= '256B'
925 # 2x32 configuration, so 2 devices
929 ranks_per_channel
= 1
931 # GDDR5 has 4 bank groups
932 bank_groups_per_rank
= 4
934 # GDDR5 has 16 banks with 4 bank groups
940 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
941 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
942 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
943 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
944 # With bank group architectures, tBURST represents the CAS-to-CAS
945 # delay for bursts to different bank groups (tCCD_S)
948 # @1000MHz data rate, tCCD_L is 3 CK
949 # CAS-to-CAS delay for bursts to the same bank group
950 # tBURST is equivalent to tCCD_S; no explicit parameter required
951 # for CAS-to-CAS delay for bursts to different bank groups
956 # tCL is not directly found in datasheet and assumed equal tRCD
962 # RRD_S (different bank group)
963 # RRD_S is 5.5 ns in datasheet.
964 # rounded to the next multiple of tCK
967 # RRD_L (same bank group)
968 # RRD_L is 5.5 ns in datasheet.
969 # rounded to the next multiple of tCK
975 # Therefore, activation limit is set to 0
981 # Here using the average of WTR_S and WTR_L
984 # Read-to-Precharge 2 CK
990 # A single HBM x128 interface (one command and address bus), with
991 # default timings based on data publically released
992 # ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
993 # IDD measurement values, and by extrapolating data from other classes.
994 # Architecture values based on published HBM spec
995 # A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
996 class HBM_1000_4H_1x128(DRAMInterface
):
997 # HBM gen1 supports up to 8 128-bit physical channels
998 # Configuration defines a single channel, with the capacity
999 # set to (full_ stack_capacity / 8) based on 2Gb dies
1000 # To use all 8 channels, set 'channels' parameter to 8 in
1001 # system configuration
1003 # 128-bit interface legacy mode
1004 device_bus_width
= 128
1006 # HBM supports BL4 and BL2 (legacy mode only)
1009 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
1010 # with 8 channels, 128MB per channel
1011 device_size
= '128MB'
1013 device_rowbuffer_size
= '2kB'
1015 # 1x128 configuration
1016 devices_per_rank
= 1
1018 # HBM does not have a CS pin; set rank to 1
1019 ranks_per_channel
= 1
1021 # HBM has 8 or 16 banks depending on capacity
1022 # 2Gb dies have 8 banks
1025 # depending on frequency, bank groups may be required
1026 # will always have 4 bank groups when enabled
1027 # current specifications do not define the minimum frequency for
1028 # bank group architecture
1029 # setting bank_groups_per_rank to 0 to disable until range is defined
1030 bank_groups_per_rank
= 0
1032 # 500 MHz for 1Gbps DDR data rate
1035 # use values from IDD measurement in JEDEC spec
1036 # use tRP value for tRCD and tCL similar to other classes
1042 # BL2 and BL4 supported, default to BL4
1043 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
1046 # value for 2Gb device from JEDEC spec
1049 # value for 2Gb device from JEDEC spec
1052 # extrapolate the following from LPDDR configs, using ns values
1053 # to minimize burst length, prefetch differences
1058 # start with 2 cycles turnaround, similar to other memory classes
1059 # could be more with variations across the stack
1062 # single rank device, set to 0
1065 # from MemCon example, tRRD is 4ns with 2ns tCK
1068 # from MemCon example, tFAW is 30ns with 2ns tCK
1070 activation_limit
= 4
1075 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1078 # A single HBM x64 interface (one command and address bus), with
1079 # default timings based on HBM gen1 and data publically released
1080 # A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1081 # Note: This defines a pseudo-channel with a unique controller
1082 # instantiated per pseudo-channel
1083 # Stay at same IO rate (1Gbps) to maintain timing relationship with
1084 # HBM gen1 class (HBM_1000_4H_x128) where possible
1085 class HBM_1000_4H_1x64(HBM_1000_4H_1x128
):
1086 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1087 # Configuration defines a single pseudo channel, with the capacity
1088 # set to (full_ stack_capacity / 16) based on 8Gb dies
1089 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1090 # system configuration
1092 # 64-bit pseudo-channle interface
1093 device_bus_width
= 64
1095 # HBM pseudo-channel only supports BL4
1098 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1099 # with 16 channels, 256MB per channel
1100 device_size
= '256MB'
1102 # page size is halved with pseudo-channel; maintaining the same same number
1103 # of rows per pseudo-channel with 2X banks across 2 channels
1104 device_rowbuffer_size
= '1kB'
1106 # HBM has 8 or 16 banks depending on capacity
1107 # Starting with 4Gb dies, 16 banks are defined
1110 # reset tRFC for larger, 8Gb device
1111 # use HBM1 4Gb value as a starting point
1114 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1116 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1120 # active powerdown and precharge powerdown exit time
1123 # self refresh exit time
1126 # A single LPDDR5 x16 interface (one command/address bus)
1127 # for a single x16 channel with default timings based on
1128 # initial JEDEC specification
1129 # Starting with 5.5Gbps data rates and 8Gbit die
1130 # Configuring for 16-bank mode with bank-group architecture
1131 # burst of 32, which means bursts can be interleaved
1132 class LPDDR5_5500_1x16_BG_BL32(DRAMInterface
):
1134 # Increase buffer size to account for more bank resources
1135 read_buffer_size
= 64
1137 # Set page policy to better suit DMC Huxley
1138 page_policy
= 'close_adaptive'
1140 # 16-bit channel interface
1141 device_bus_width
= 16
1143 # LPDDR5 is a BL16 or BL32 device
1144 # With BG mode, BL16 and BL32 are supported
1145 # Use BL32 for higher command bandwidth
1148 # size of device in bytes
1151 # 2kB page with BG mode
1152 device_rowbuffer_size
= '2kB'
1154 # Use a 1x16 configuration
1155 devices_per_rank
= 1
1158 ranks_per_channel
= 1
1160 # LPDDR5 supports configurable bank options
1161 # 8B : BL32, all frequencies
1162 # 16B : BL32 or BL16, <=3.2Gbps
1163 # 16B with Bank Group Arch (4B/BG): BL32 or BL16, >3.2Gbps
1164 # Initial configuration will have 16 banks with Bank Group Arch
1165 # to maximim resources and enable higher data rates
1167 bank_groups_per_rank
= 4
1169 # 5.5Gb/s DDR with 4:1 WCK:CK ratio for 687.5 MHz CK
1172 # Greater of 2 CK or 18ns
1175 # Base RL is 16 CK @ 687.5 MHz = 23.28ns
1178 # Greater of 2 CK or 18ns
1181 # Greater of 3 CK or 42ns
1184 # Greater of 3 CK or 34ns
1187 # active powerdown and precharge powerdown exit time
1188 # Greater of 3 CK or 7ns
1191 # self refresh exit time (tRFCab + 7.5ns)
1194 # Greater of 2 CK or 7.5 ns minus 2 CK
1197 # With BG architecture, burst of 32 transferred in two 16-beat
1198 # sub-bursts, with a 16-beat gap in between.
1199 # Each 16-beat sub-burst is 8 WCK @2.75 GHz or 2 CK @ 687.5 MHz
1200 # tBURST is the delay to transfer the Bstof32 = 6 CK @ 687.5 MHz
1202 # can interleave a Bstof32 from another bank group at tBURST_MIN
1203 # 16-beats is 8 WCK @2.75 GHz or 2 CK @ 687.5 MHz
1204 tBURST_MIN
= '2.91ns'
1205 # tBURST_MAX is the maximum burst delay for same bank group timing
1206 # this is 8 CK @ 687.5 MHz
1207 tBURST_MAX
= '11.64ns'
1212 # LPDDR5, 8 Gbit/channel for 280ns tRFCab
1216 # Greater of 4 CK or 6.25 ns
1218 # Greater of 4 CK or 12 ns
1221 # Required RD-to-WR timing is RL+ BL/n + tWCKDQ0/tCK - WL
1222 # tWCKDQ0/tCK will be 1 CK for most cases
1223 # For gem5 RL = WL and BL/n is already accounted for with tBURST
1224 # Result is and additional 1 CK is required
1227 # Default different rank bus delay to 2 CK, @687.5 MHz = 2.91 ns
1233 # Greater of 2 CK or 5 ns
1237 # With Bank Group Arch mode tFAW is 20 ns
1239 activation_limit
= 4
1241 # at 5Gbps, 4:1 WCK to CK ratio required
1242 # 2 data beats per WCK (DDR) -> 8 per CK
1245 # 2 cycles required to send activate command
1246 # 2 command phases can be sent back-to-back or
1247 # with a gap up to tAAD = 8 CK
1248 two_cycle_activate
= True
1251 data_clock_sync
= True
1253 # A single LPDDR5 x16 interface (one command/address bus)
1254 # for a single x16 channel with default timings based on
1255 # initial JEDEC specification
1256 # Starting with 5.5Gbps data rates and 8Gbit die
1257 # Configuring for 16-bank mode with bank-group architecture, burst of 16
1258 class LPDDR5_5500_1x16_BG_BL16(LPDDR5_5500_1x16_BG_BL32
):
1260 # LPDDR5 is a BL16 or BL32 device
1261 # With BG mode, BL16 and BL32 are supported
1262 # Use BL16 for smaller access granularity
1265 # For Bstof16 with BG arch, 2 CK @ 687.5 MHz with 4:1 clock ratio
1267 tBURST_MIN
= '2.91ns'
1268 # For Bstof16 with BG arch, 4 CK @ 687.5 MHz with 4:1 clock ratio
1269 tBURST_MAX
= '5.82ns'
1275 # A single LPDDR5 x16 interface (one command/address bus)
1276 # for a single x16 channel with default timings based on
1277 # initial JEDEC specification
1278 # Starting with 5.5Gbps data rates and 8Gbit die
1279 # Configuring for 8-bank mode, burst of 32
1280 class LPDDR5_5500_1x16_8B_BL32(LPDDR5_5500_1x16_BG_BL32
):
1282 # 4kB page with 8B mode
1283 device_rowbuffer_size
= '4kB'
1285 # LPDDR5 supports configurable bank options
1286 # 8B : BL32, all frequencies
1287 # 16B : BL32 or BL16, <=3.2Gbps
1288 # 16B with Bank Group Arch (4B/BG): BL32 or BL16, >3.2Gbps
1291 bank_groups_per_rank
= 0
1293 # For Bstof32 with 8B mode, 4 CK @ 687.5 MHz with 4:1 clock ratio
1295 tBURST_MIN
= '5.82ns'
1296 tBURST_MAX
= '5.82ns'
1298 # Greater of 4 CK or 12 ns
1301 # Greater of 2 CK or 10 ns
1304 # With 8B mode tFAW is 40 ns
1306 activation_limit
= 4
1308 # Reset BG arch timing for 8B mode
1313 # A single LPDDR5 x16 interface (one command/address bus)
1314 # for a single x16 channel with default timings based on
1315 # initial JEDEC specification
1316 # 6.4Gbps data rates and 8Gbit die
1317 # Configuring for 16-bank mode with bank-group architecture
1318 # burst of 32, which means bursts can be interleaved
1319 class LPDDR5_6400_1x16_BG_BL32(LPDDR5_5500_1x16_BG_BL32
):
1321 # 5.5Gb/s DDR with 4:1 WCK:CK ratio for 687.5 MHz CK
1324 # Base RL is 17 CK @ 800 MHz = 21.25ns
1327 # With BG architecture, burst of 32 transferred in two 16-beat
1328 # sub-bursts, with a 16-beat gap in between.
1329 # Each 16-beat sub-burst is 8 WCK @3.2 GHz or 2 CK @ 800 MHz
1330 # tBURST is the delay to transfer the Bstof32 = 6 CK @ 800 MHz
1332 # can interleave a Bstof32 from another bank group at tBURST_MIN
1333 # 16-beats is 8 WCK @2.3 GHz or 2 CK @ 800 MHz
1334 tBURST_MIN
= '2.5ns'
1335 # tBURST_MAX is the maximum burst delay for same bank group timing
1336 # this is 8 CK @ 800 MHz
1342 # Required RD-to-WR timing is RL+ BL/n + tWCKDQ0/tCK - WL
1343 # tWCKDQ0/tCK will be 1 CK for most cases
1344 # For gem5 RL = WL and BL/n is already accounted for with tBURST
1345 # Result is and additional 1 CK is required
1348 # Default different rank bus delay to 2 CK, @687.5 MHz = 2.5 ns
1354 # 2 command phases can be sent back-to-back or
1355 # with a gap up to tAAD = 8 CK
1358 # A single LPDDR5 x16 interface (one command/address bus)
1359 # for a single x16 channel with default timings based on initial
1360 # JEDEC specifcation
1361 # 6.4Gbps data rates and 8Gbit die
1362 # Configuring for 16-bank mode with bank-group architecture, burst of 16
1363 class LPDDR5_6400_1x16_BG_BL16(LPDDR5_6400_1x16_BG_BL32
):
1365 # LPDDR5 is a BL16 or BL32 device
1366 # With BG mode, BL16 and BL32 are supported
1367 # Use BL16 for smaller access granularity
1370 # For Bstof16 with BG arch, 2 CK @ 800 MHz with 4:1 clock ratio
1372 tBURST_MIN
= '2.5ns'
1373 # For Bstof16 with BG arch, 4 CK @ 800 MHz with 4:1 clock ratio
1380 # A single LPDDR5 x16 interface (one command/address bus)
1381 # for a single x16 channel with default timings based on
1382 # initial JEDEC specification
1383 # 6.4Gbps data rates and 8Gbit die
1384 # Configuring for 8-bank mode, burst of 32
1385 class LPDDR5_6400_1x16_8B_BL32(LPDDR5_6400_1x16_BG_BL32
):
1387 # 4kB page with 8B mode
1388 device_rowbuffer_size
= '4kB'
1390 # LPDDR5 supports configurable bank options
1391 # 8B : BL32, all frequencies
1392 # 16B : BL32 or BL16, <=3.2Gbps
1393 # 16B with Bank Group Arch (4B/BG): BL32 or BL16, >3.2Gbps
1396 bank_groups_per_rank
= 0
1398 # For Bstof32 with 8B mode, 4 CK @ 800 MHz with 4:1 clock ratio
1403 # Greater of 4 CK or 12 ns
1406 # Greater of 2 CK or 10 ns
1409 # With 8B mode tFAW is 40 ns
1411 activation_limit
= 4
1413 # Reset BG arch timing for 8B mode