1 # Copyright (c) 2012-2020 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2013 Amin Farmahini-Farahani
14 # Copyright (c) 2015 University of Kaiserslautern
15 # Copyright (c) 2015 The University of Bologna
16 # All rights reserved.
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19 # modification, are permitted provided that the following conditions are
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41 from m5
.params
import *
42 from m5
.proxy
import *
44 from m5
.objects
.AbstractMemory
import AbstractMemory
46 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
47 # channel, rank, bank, row and column, respectively, and going from
48 # MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
49 # suitable for an open-page policy, optimising for sequential accesses
50 # hitting in the open row. For a closed-page policy, RoCoRaBaCh
51 # maximises parallelism.
52 class AddrMap(Enum
): vals
= ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
54 # Enum for the page policy, either open, open_adaptive, close, or
56 class PageManage(Enum
): vals
= ['open', 'open_adaptive', 'close',
59 class DRAMInterface(AbstractMemory
):
60 type = 'DRAMInterface'
61 cxx_header
= "mem/dram_ctrl.hh"
63 # Allow the interface to set required controller buffer sizes
64 # each entry corresponds to a burst for the specific DRAM
65 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
66 # the cacheline size or request/packet size
67 write_buffer_size
= Param
.Unsigned(64, "Number of write queue entries")
68 read_buffer_size
= Param
.Unsigned(32, "Number of read queue entries")
70 # scheduler, address map and page policy
71 addr_mapping
= Param
.AddrMap('RoRaBaCoCh', "Address mapping policy")
72 page_policy
= Param
.PageManage('open_adaptive', "Page management policy")
74 # enforce a limit on the number of accesses per row
75 max_accesses_per_row
= Param
.Unsigned(16, "Max accesses per row before "
78 # size of DRAM Chip in Bytes
79 device_size
= Param
.MemorySize("Size of DRAM chip")
80 # the physical organisation of the DRAM
81 device_bus_width
= Param
.Unsigned("data bus width in bits for each DRAM "\
83 burst_length
= Param
.Unsigned("Burst lenght (BL) in beats")
84 device_rowbuffer_size
= Param
.MemorySize("Page (row buffer) size per "\
86 devices_per_rank
= Param
.Unsigned("Number of devices/chips per rank")
87 ranks_per_channel
= Param
.Unsigned("Number of ranks per channel")
89 # default to 0 bank groups per rank, indicating bank group architecture
91 # update per memory class when bank group architecture is supported
92 bank_groups_per_rank
= Param
.Unsigned(0, "Number of bank groups per rank")
93 banks_per_rank
= Param
.Unsigned("Number of banks per rank")
95 # Enable DRAM powerdown states if True. This is False by default due to
96 # performance being lower when enabled
97 enable_dram_powerdown
= Param
.Bool(False, "Enable powerdown states")
99 # For power modelling we need to know if the DRAM has a DLL or not
100 dll
= Param
.Bool(True, "DRAM has DLL or not")
102 # DRAMPower provides in addition to the core power, the possibility to
103 # include RD/WR termination and IO power. This calculation assumes some
104 # default values. The integration of DRAMPower with gem5 does not include
105 # IO and RD/WR termination power by default. This might be added as an
106 # additional feature in the future.
108 # timing behaviour and constraints - all in nanoseconds
110 # the base clock period of the DRAM
111 tCK
= Param
.Latency("Clock period")
113 # the amount of time in nanoseconds from issuing an activate command
114 # to the data being available in the row buffer for a read/write
115 tRCD
= Param
.Latency("RAS to CAS delay")
117 # the time from issuing a read/write command to seeing the actual data
118 tCL
= Param
.Latency("CAS latency")
120 # minimum time between a precharge and subsequent activate
121 tRP
= Param
.Latency("Row precharge time")
123 # minimum time between an activate and a precharge to the same row
124 tRAS
= Param
.Latency("ACT to PRE delay")
126 # minimum time between a write data transfer and a precharge
127 tWR
= Param
.Latency("Write recovery time")
129 # minimum time between a read and precharge command
130 tRTP
= Param
.Latency("Read to precharge")
132 # time to complete a burst transfer, typically the burst length
133 # divided by two due to the DDR bus, but by making it a parameter
134 # it is easier to also evaluate SDR memories like WideIO.
135 # This parameter has to account for burst length.
136 # Read/Write requests with data size larger than one full burst are broken
137 # down into multiple requests in the controller
138 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
139 # With bank group architectures, tBURST represents the CAS-to-CAS
140 # delay for bursts to different bank groups (tCCD_S)
141 tBURST
= Param
.Latency("Burst duration "
142 "(typically burst length / 2 cycles)")
144 # tBURST_MAX is the column array cycle delay required before next access,
145 # which could be greater than tBURST when the memory access time is greater
147 tBURST_MAX
= Param
.Latency(Self
.tBURST
, "Column access delay")
149 # tBURST_MIN is the minimum delay between bursts, which could be less than
150 # tBURST when interleaving is supported
151 tBURST_MIN
= Param
.Latency(Self
.tBURST
, "Minimim delay between bursts")
153 # CAS-to-CAS delay for bursts to the same bank group
154 # only utilized with bank group architectures; set to 0 for default case
155 # tBURST is equivalent to tCCD_S; no explicit parameter required
156 # for CAS-to-CAS delay for bursts to different bank groups
157 tCCD_L
= Param
.Latency("0ns", "Same bank group CAS to CAS delay")
159 # Write-to-Write delay for bursts to the same bank group
160 # only utilized with bank group architectures; set to 0 for default case
161 # This will be used to enable different same bank group delays
162 # for writes versus reads
163 tCCD_L_WR
= Param
.Latency(Self
.tCCD_L
,
164 "Same bank group Write to Write delay")
166 # time taken to complete one refresh cycle (N rows in all banks)
167 tRFC
= Param
.Latency("Refresh cycle time")
169 # refresh command interval, how often a "ref" command needs
170 # to be sent. It is 7.8 us for a 64ms refresh requirement
171 tREFI
= Param
.Latency("Refresh command interval")
173 # write-to-read, same rank turnaround penalty
174 tWTR
= Param
.Latency("Write to read, same rank switching time")
176 # write-to-read, same rank turnaround penalty for same bank group
177 tWTR_L
= Param
.Latency(Self
.tWTR
, "Write to read, same rank switching "
178 "time, same bank group")
180 # read-to-write, same rank turnaround penalty
181 tRTW
= Param
.Latency("Read to write, same rank switching time")
183 # rank-to-rank bus delay penalty
184 # this does not correlate to a memory timing parameter and encompasses:
185 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
186 # different rank bus delay
187 tCS
= Param
.Latency("Rank to rank switching time")
189 # minimum precharge to precharge delay time
190 tPPD
= Param
.Latency("0ns", "PRE to PRE delay")
192 # maximum delay between two-cycle ACT command phases
193 tAAD
= Param
.Latency(Self
.tCK
,
194 "Maximum delay between two-cycle ACT commands")
196 two_cycle_activate
= Param
.Bool(False,
197 "Two cycles required to send activate")
199 # minimum row activate to row activate delay time
200 tRRD
= Param
.Latency("ACT to ACT delay")
202 # only utilized with bank group architectures; set to 0 for default case
203 tRRD_L
= Param
.Latency("0ns", "Same bank group ACT to ACT delay")
205 # time window in which a maximum number of activates are allowed
206 # to take place, set to 0 to disable
207 tXAW
= Param
.Latency("X activation window")
208 activation_limit
= Param
.Unsigned("Max number of activates in window")
210 # time to exit power-down mode
211 # Exit power-down to next valid command delay
212 tXP
= Param
.Latency("0ns", "Power-up Delay")
214 # Exit Powerdown to commands requiring a locked DLL
215 tXPDLL
= Param
.Latency("0ns", "Power-up Delay with locked DLL")
217 # time to exit self-refresh mode
218 tXS
= Param
.Latency("0ns", "Self-refresh exit latency")
220 # time to exit self-refresh mode with locked DLL
221 tXSDLL
= Param
.Latency("0ns", "Self-refresh exit latency DLL")
223 # number of data beats per clock. with DDR, default is 2, one per edge
224 beats_per_clock
= Param
.Unsigned(2, "Data beats per clock")
226 data_clock_sync
= Param
.Bool(False, "Synchronization commands required")
228 # Currently rolled into other params
229 ######################################################################
231 # tRC - assumed to be tRAS + tRP
233 # Power Behaviour and Constraints
234 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
235 # defined as VDD and VDD2. Each current is defined for each voltage domain
236 # separately. For example, current IDD0 is active-precharge current for
237 # voltage domain VDD and current IDD02 is active-precharge current for
238 # voltage domain VDD2.
239 # By default all currents are set to 0mA. Users who are only interested in
240 # the performance of DRAMs can leave them at 0.
242 # Operating 1 Bank Active-Precharge current
243 IDD0
= Param
.Current("0mA", "Active precharge current")
245 # Operating 1 Bank Active-Precharge current multiple voltage Range
246 IDD02
= Param
.Current("0mA", "Active precharge current VDD2")
248 # Precharge Power-down Current: Slow exit
249 IDD2P0
= Param
.Current("0mA", "Precharge Powerdown slow")
251 # Precharge Power-down Current: Slow exit multiple voltage Range
252 IDD2P02
= Param
.Current("0mA", "Precharge Powerdown slow VDD2")
254 # Precharge Power-down Current: Fast exit
255 IDD2P1
= Param
.Current("0mA", "Precharge Powerdown fast")
257 # Precharge Power-down Current: Fast exit multiple voltage Range
258 IDD2P12
= Param
.Current("0mA", "Precharge Powerdown fast VDD2")
260 # Precharge Standby current
261 IDD2N
= Param
.Current("0mA", "Precharge Standby current")
263 # Precharge Standby current multiple voltage range
264 IDD2N2
= Param
.Current("0mA", "Precharge Standby current VDD2")
266 # Active Power-down current: slow exit
267 IDD3P0
= Param
.Current("0mA", "Active Powerdown slow")
269 # Active Power-down current: slow exit multiple voltage range
270 IDD3P02
= Param
.Current("0mA", "Active Powerdown slow VDD2")
272 # Active Power-down current : fast exit
273 IDD3P1
= Param
.Current("0mA", "Active Powerdown fast")
275 # Active Power-down current : fast exit multiple voltage range
276 IDD3P12
= Param
.Current("0mA", "Active Powerdown fast VDD2")
278 # Active Standby current
279 IDD3N
= Param
.Current("0mA", "Active Standby current")
281 # Active Standby current multiple voltage range
282 IDD3N2
= Param
.Current("0mA", "Active Standby current VDD2")
284 # Burst Read Operating Current
285 IDD4R
= Param
.Current("0mA", "READ current")
287 # Burst Read Operating Current multiple voltage range
288 IDD4R2
= Param
.Current("0mA", "READ current VDD2")
290 # Burst Write Operating Current
291 IDD4W
= Param
.Current("0mA", "WRITE current")
293 # Burst Write Operating Current multiple voltage range
294 IDD4W2
= Param
.Current("0mA", "WRITE current VDD2")
297 IDD5
= Param
.Current("0mA", "Refresh current")
299 # Refresh Current multiple voltage range
300 IDD52
= Param
.Current("0mA", "Refresh current VDD2")
302 # Self-Refresh Current
303 IDD6
= Param
.Current("0mA", "Self-refresh Current")
305 # Self-Refresh Current multiple voltage range
306 IDD62
= Param
.Current("0mA", "Self-refresh Current VDD2")
308 # Main voltage range of the DRAM
309 VDD
= Param
.Voltage("0V", "Main Voltage Range")
311 # Second voltage range defined by some DRAMs
312 VDD2
= Param
.Voltage("0V", "2nd Voltage Range")
314 # A single DDR3-1600 x64 channel (one command and address bus), with
315 # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
316 # an 8x8 configuration.
317 class DDR3_1600_8x8(DRAMInterface
):
318 # size of device in bytes
319 device_size
= '512MB'
321 # 8x8 configuration, 8 devices each with an 8-bit interface
324 # DDR3 is a BL8 device
327 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
328 device_rowbuffer_size
= '1kB'
330 # 8x8 configuration, so 8 devices
334 ranks_per_channel
= 2
336 # DDR3 has 8 banks in all configurations
342 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
357 # Greater of 4 CK or 7.5 ns
360 # Greater of 4 CK or 7.5 ns
363 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
366 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
369 # <=85C, half for >85C
372 # active powerdown and precharge powerdown exit time
375 # self refresh exit time
378 # Current values from datasheet Die Rev E,J
390 # A single HMC-2500 x32 model based on:
391 # [1] DRAMSpec: a high-level DRAM bank modelling tool
392 # developed at the University of Kaiserslautern. This high level tool
393 # uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
394 # estimate the DRAM bank latency and power numbers.
395 # [2] High performance AXI-4.0 based interconnect for extensible smart memory
396 # cubes (E. Azarkhish et. al)
397 # Assumed for the HMC model is a 30 nm technology node.
398 # The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
400 # Each layer has 16 vaults and each vault consists of 2 banks per layer.
401 # In order to be able to use the same controller used for 2D DRAM generations
402 # for HMC, the following analogy is done:
403 # Channel (DDR) => Vault (HMC)
404 # device_size (DDR) => size of a single layer in a vault
405 # ranks per channel (DDR) => number of layers
406 # banks per rank (DDR) => banks per layer
407 # devices per rank (DDR) => devices per layer ( 1 for HMC).
408 # The parameters for which no input is available are inherited from the DDR3
410 # This configuration includes the latencies from the DRAM to the logic layer
412 class HMC_2500_1x32(DDR3_1600_8x8
):
414 # two banks per device with each bank 4MB [2]
417 # 1x32 configuration, 1 device with 32 TSVs [2]
418 device_bus_width
= 32
420 # HMC is a BL8 device [2]
423 # Each device has a page (row buffer) size of 256 bytes [2]
424 device_rowbuffer_size
= '256B'
426 # 1x32 configuration, so 1 device [2]
429 # 4 layers so 4 ranks [2]
430 ranks_per_channel
= 4
432 # HMC has 2 banks per layer [2]
433 # Each layer represents a rank. With 4 layers and 8 banks in total, each
434 # layer has 2 banks; thus 2 banks per rank.
440 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
443 # Values using DRAMSpec HMC model [1]
449 # tRRD depends on the power supply network for each vendor.
450 # We assume a tRRD of a double bank approach to be equal to 4 clock
451 # cycles (Assumption)
454 # activation limit is set to 0 since there are only 2 banks per vault
458 # Values using DRAMSpec HMC model [1]
463 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
464 # 0.8 ns (Assumption)
467 # Value using DRAMSpec HMC model [1]
470 # The default page policy in the vault controllers is simple closed page
471 # [2] nevertheless 'close' policy opens and closes the row multiple times
472 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
473 page_policy
= 'close_adaptive'
475 # RoCoRaBaCh resembles the default address mapping in HMC
476 addr_mapping
= 'RoCoRaBaCh'
478 # These parameters do not directly correlate with buffer_size in real
479 # hardware. Nevertheless, their value has been tuned to achieve a
480 # bandwidth similar to the cycle-accurate model in [2]
481 write_buffer_size
= 32
482 read_buffer_size
= 32
484 # A single DDR3-2133 x64 channel refining a selected subset of the
485 # options for the DDR-1600 configuration, based on the same DDR3-1600
486 # 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
487 # consistent across the two configurations.
488 class DDR3_2133_8x8(DDR3_1600_8x8
):
492 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
503 # Current values from datasheet
515 # A single DDR4-2400 x64 channel (one command and address bus), with
516 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
517 # in an 16x4 configuration.
518 # Total channel capacity is 32GB
519 # 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
520 class DDR4_2400_16x4(DRAMInterface
):
524 # 16x4 configuration, 16 devices each with a 4-bit interface
527 # DDR4 is a BL8 device
530 # Each device has a page (row buffer) size of 512 byte (1K columns x4)
531 device_rowbuffer_size
= '512B'
533 # 16x4 configuration, so 16 devices
534 devices_per_rank
= 16
536 # Match our DDR3 configurations which is dual rank
537 ranks_per_channel
= 2
539 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
540 # Set to 4 for x4 case
541 bank_groups_per_rank
= 4
543 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
544 # configurations). Currently we do not capture the additional
545 # constraints incurred by the bank groups
548 # override the default buffer sizes and go for something larger to
549 # accommodate the larger bank count
550 write_buffer_size
= 128
551 read_buffer_size
= 64
556 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
557 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
558 # With bank group architectures, tBURST represents the CAS-to-CAS
559 # delay for bursts to different bank groups (tCCD_S)
562 # @2400 data rate, tCCD_L is 6 CK
563 # CAS-to-CAS delay for bursts to the same bank group
564 # tBURST is equivalent to tCCD_S; no explicit parameter required
565 # for CAS-to-CAS delay for bursts to different bank groups
574 # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
577 # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
580 # tFAW for 512B page is MAX(16 CK, 13ns)
588 # Here using the average of WTR_S and WTR_L
591 # Greater of 4 CK or 7.5 ns
594 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
597 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
600 # <=85C, half for >85C
603 # active powerdown and precharge powerdown exit time
606 # self refresh exit time
607 # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
608 # tRFC + 10ns = 340ns
611 # Current values from datasheet
626 # A single DDR4-2400 x64 channel (one command and address bus), with
627 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
628 # in an 8x8 configuration.
629 # Total channel capacity is 16GB
630 # 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
631 class DDR4_2400_8x8(DDR4_2400_16x4
):
632 # 8x8 configuration, 8 devices each with an 8-bit interface
635 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
636 device_rowbuffer_size
= '1kB'
638 # 8x8 configuration, so 8 devices
641 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
646 # Current values from datasheet
653 # A single DDR4-2400 x64 channel (one command and address bus), with
654 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
655 # in an 4x16 configuration.
656 # Total channel capacity is 4GB
657 # 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
658 class DDR4_2400_4x16(DDR4_2400_16x4
):
659 # 4x16 configuration, 4 devices each with an 16-bit interface
660 device_bus_width
= 16
662 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
663 device_rowbuffer_size
= '2kB'
665 # 4x16 configuration, so 4 devices
668 # Single rank for x16
669 ranks_per_channel
= 1
671 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
672 # Set to 2 for x16 case
673 bank_groups_per_rank
= 2
675 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
676 # configurations). Currently we do not capture the additional
677 # constraints incurred by the bank groups
680 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
683 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
688 # Current values from datasheet
698 # A single LPDDR2-S4 x32 interface (one command/address bus), with
699 # default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
700 # in a 1x32 configuration.
701 class LPDDR2_S4_1066_1x32(DRAMInterface
):
706 device_size
= '512MB'
708 # 1x32 configuration, 1 device with a 32-bit interface
709 device_bus_width
= 32
711 # LPDDR2_S4 is a BL4 and BL8 device
714 # Each device has a page (row buffer) size of 1KB
715 # (this depends on the memory density)
716 device_rowbuffer_size
= '1kB'
718 # 1x32 configuration, so 1 device
722 ranks_per_channel
= 1
724 # LPDDR2-S4 has 8 banks in all configurations
733 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
736 # Pre-charge one bank 15 ns (all banks 18 ns)
744 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
745 # Note this is a BL8 DDR device.
746 # Requests larger than 32 bytes are broken down into multiple requests
754 # active powerdown and precharge powerdown exit time
757 # self refresh exit time
760 # Irrespective of speed grade, tWTR is 7.5 ns
763 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
766 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
769 # Activate to activate irrespective of density and speed grade
772 # Irrespective of density, tFAW is 50 ns
776 # Current values from datasheet
798 # A single WideIO x128 interface (one command and address bus), with
799 # default timings based on an estimated WIO-200 8 Gbit part.
800 class WideIO_200_1x128(DRAMInterface
):
805 device_size
= '1024MB'
807 # 1x128 configuration, 1 device with a 128-bit interface
808 device_bus_width
= 128
810 # This is a BL4 device
813 # Each device has a page (row buffer) size of 4KB
814 # (this depends on the memory density)
815 device_rowbuffer_size
= '4kB'
817 # 1x128 configuration, so 1 device
820 # Use one rank for a one-high die stack
821 ranks_per_channel
= 1
823 # WideIO has 4 banks in all configurations
835 # Read to precharge is same as the burst
838 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
839 # Note this is a BL4 SDR device.
845 # WIO 8 Gb, <=85C, half for >85C
848 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
851 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
854 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
857 # Activate to activate irrespective of density and speed grade
860 # Two instead of four activation window
864 # The WideIO specification does not provide current information
866 # A single LPDDR3 x32 interface (one command/address bus), with
867 # default timings based on a LPDDR3-1600 4 Gbit part (Micron
868 # EDF8132A1MC) in a 1x32 configuration.
869 class LPDDR3_1600_1x32(DRAMInterface
):
874 device_size
= '512MB'
876 # 1x32 configuration, 1 device with a 32-bit interface
877 device_bus_width
= 32
879 # LPDDR3 is a BL8 device
882 # Each device has a page (row buffer) size of 4KB
883 device_rowbuffer_size
= '4kB'
885 # 1x32 configuration, so 1 device
888 # Technically the datasheet is a dual-rank package, but for
889 # comparison with the LPDDR2 config we stick to a single rank
890 ranks_per_channel
= 1
892 # LPDDR3 has 8 banks in all configurations
900 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
906 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
909 # Pre-charge one bank 18 ns (all banks 21 ns)
912 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
913 # Note this is a BL8 DDR device.
914 # Requests larger than 32 bytes are broken down into multiple requests
922 # active powerdown and precharge powerdown exit time
925 # self refresh exit time
928 # Irrespective of speed grade, tWTR is 7.5 ns
931 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
934 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
937 # Activate to activate irrespective of density and speed grade
940 # Irrespective of size, tFAW is 50 ns
944 # Current values from datasheet
966 # A single GDDR5 x64 interface, with
967 # default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
968 # H5GQ1H24AFR) in a 2x32 configuration.
969 class GDDR5_4000_2x32(DRAMInterface
):
971 device_size
= '128MB'
973 # 2x32 configuration, 1 device with a 32-bit interface
974 device_bus_width
= 32
976 # GDDR5 is a BL8 device
979 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
980 device_rowbuffer_size
= '256B'
982 # 2x32 configuration, so 2 devices
986 ranks_per_channel
= 1
988 # GDDR5 has 4 bank groups
989 bank_groups_per_rank
= 4
991 # GDDR5 has 16 banks with 4 bank groups
997 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
998 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
999 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
1000 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
1001 # With bank group architectures, tBURST represents the CAS-to-CAS
1002 # delay for bursts to different bank groups (tCCD_S)
1005 # @1000MHz data rate, tCCD_L is 3 CK
1006 # CAS-to-CAS delay for bursts to the same bank group
1007 # tBURST is equivalent to tCCD_S; no explicit parameter required
1008 # for CAS-to-CAS delay for bursts to different bank groups
1013 # tCL is not directly found in datasheet and assumed equal tRCD
1019 # RRD_S (different bank group)
1020 # RRD_S is 5.5 ns in datasheet.
1021 # rounded to the next multiple of tCK
1024 # RRD_L (same bank group)
1025 # RRD_L is 5.5 ns in datasheet.
1026 # rounded to the next multiple of tCK
1032 # Therefore, activation limit is set to 0
1033 activation_limit
= 0
1038 # Here using the average of WTR_S and WTR_L
1041 # Read-to-Precharge 2 CK
1047 # A single HBM x128 interface (one command and address bus), with
1048 # default timings based on data publically released
1049 # ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
1050 # IDD measurement values, and by extrapolating data from other classes.
1051 # Architecture values based on published HBM spec
1052 # A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
1053 class HBM_1000_4H_1x128(DRAMInterface
):
1054 # HBM gen1 supports up to 8 128-bit physical channels
1055 # Configuration defines a single channel, with the capacity
1056 # set to (full_ stack_capacity / 8) based on 2Gb dies
1057 # To use all 8 channels, set 'channels' parameter to 8 in
1058 # system configuration
1060 # 128-bit interface legacy mode
1061 device_bus_width
= 128
1063 # HBM supports BL4 and BL2 (legacy mode only)
1066 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
1067 # with 8 channels, 128MB per channel
1068 device_size
= '128MB'
1070 device_rowbuffer_size
= '2kB'
1072 # 1x128 configuration
1073 devices_per_rank
= 1
1075 # HBM does not have a CS pin; set rank to 1
1076 ranks_per_channel
= 1
1078 # HBM has 8 or 16 banks depending on capacity
1079 # 2Gb dies have 8 banks
1082 # depending on frequency, bank groups may be required
1083 # will always have 4 bank groups when enabled
1084 # current specifications do not define the minimum frequency for
1085 # bank group architecture
1086 # setting bank_groups_per_rank to 0 to disable until range is defined
1087 bank_groups_per_rank
= 0
1089 # 500 MHz for 1Gbps DDR data rate
1092 # use values from IDD measurement in JEDEC spec
1093 # use tRP value for tRCD and tCL similar to other classes
1099 # BL2 and BL4 supported, default to BL4
1100 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
1103 # value for 2Gb device from JEDEC spec
1106 # value for 2Gb device from JEDEC spec
1109 # extrapolate the following from LPDDR configs, using ns values
1110 # to minimize burst length, prefetch differences
1115 # start with 2 cycles turnaround, similar to other memory classes
1116 # could be more with variations across the stack
1119 # single rank device, set to 0
1122 # from MemCon example, tRRD is 4ns with 2ns tCK
1125 # from MemCon example, tFAW is 30ns with 2ns tCK
1127 activation_limit
= 4
1132 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1135 # A single HBM x64 interface (one command and address bus), with
1136 # default timings based on HBM gen1 and data publically released
1137 # A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1138 # Note: This defines a pseudo-channel with a unique controller
1139 # instantiated per pseudo-channel
1140 # Stay at same IO rate (1Gbps) to maintain timing relationship with
1141 # HBM gen1 class (HBM_1000_4H_x128) where possible
1142 class HBM_1000_4H_1x64(HBM_1000_4H_1x128
):
1143 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1144 # Configuration defines a single pseudo channel, with the capacity
1145 # set to (full_ stack_capacity / 16) based on 8Gb dies
1146 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1147 # system configuration
1149 # 64-bit pseudo-channle interface
1150 device_bus_width
= 64
1152 # HBM pseudo-channel only supports BL4
1155 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1156 # with 16 channels, 256MB per channel
1157 device_size
= '256MB'
1159 # page size is halved with pseudo-channel; maintaining the same same number
1160 # of rows per pseudo-channel with 2X banks across 2 channels
1161 device_rowbuffer_size
= '1kB'
1163 # HBM has 8 or 16 banks depending on capacity
1164 # Starting with 4Gb dies, 16 banks are defined
1167 # reset tRFC for larger, 8Gb device
1168 # use HBM1 4Gb value as a starting point
1171 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1173 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1177 # active powerdown and precharge powerdown exit time
1180 # self refresh exit time
1183 # A single LPDDR5 x16 interface (one command/address bus)
1184 # for a single x16 channel with default timings based on
1185 # initial JEDEC specification
1186 # Starting with 5.5Gbps data rates and 8Gbit die
1187 # Configuring for 16-bank mode with bank-group architecture
1188 # burst of 32, which means bursts can be interleaved
1189 class LPDDR5_5500_1x16_BG_BL32(DRAMInterface
):
1191 # Increase buffer size to account for more bank resources
1192 read_buffer_size
= 64
1194 # Set page policy to better suit DMC Huxley
1195 page_policy
= 'close_adaptive'
1197 # 16-bit channel interface
1198 device_bus_width
= 16
1200 # LPDDR5 is a BL16 or BL32 device
1201 # With BG mode, BL16 and BL32 are supported
1202 # Use BL32 for higher command bandwidth
1205 # size of device in bytes
1208 # 2kB page with BG mode
1209 device_rowbuffer_size
= '2kB'
1211 # Use a 1x16 configuration
1212 devices_per_rank
= 1
1215 ranks_per_channel
= 1
1217 # LPDDR5 supports configurable bank options
1218 # 8B : BL32, all frequencies
1219 # 16B : BL32 or BL16, <=3.2Gbps
1220 # 16B with Bank Group Arch (4B/BG): BL32 or BL16, >3.2Gbps
1221 # Initial configuration will have 16 banks with Bank Group Arch
1222 # to maximim resources and enable higher data rates
1224 bank_groups_per_rank
= 4
1226 # 5.5Gb/s DDR with 4:1 WCK:CK ratio for 687.5 MHz CK
1229 # Greater of 2 CK or 18ns
1232 # Base RL is 16 CK @ 687.5 MHz = 23.28ns
1235 # Greater of 2 CK or 18ns
1238 # Greater of 3 CK or 42ns
1241 # Greater of 3 CK or 34ns
1244 # active powerdown and precharge powerdown exit time
1245 # Greater of 3 CK or 7ns
1248 # self refresh exit time (tRFCab + 7.5ns)
1251 # Greater of 2 CK or 7.5 ns minus 2 CK
1254 # With BG architecture, burst of 32 transferred in two 16-beat
1255 # sub-bursts, with a 16-beat gap in between.
1256 # Each 16-beat sub-burst is 8 WCK @2.75 GHz or 2 CK @ 687.5 MHz
1257 # tBURST is the delay to transfer the Bstof32 = 6 CK @ 687.5 MHz
1259 # can interleave a Bstof32 from another bank group at tBURST_MIN
1260 # 16-beats is 8 WCK @2.75 GHz or 2 CK @ 687.5 MHz
1261 tBURST_MIN
= '2.91ns'
1262 # tBURST_MAX is the maximum burst delay for same bank group timing
1263 # this is 8 CK @ 687.5 MHz
1264 tBURST_MAX
= '11.64ns'
1269 # LPDDR5, 8 Gbit/channel for 280ns tRFCab
1273 # Greater of 4 CK or 6.25 ns
1275 # Greater of 4 CK or 12 ns
1278 # Required RD-to-WR timing is RL+ BL/n + tWCKDQ0/tCK - WL
1279 # tWCKDQ0/tCK will be 1 CK for most cases
1280 # For gem5 RL = WL and BL/n is already accounted for with tBURST
1281 # Result is and additional 1 CK is required
1284 # Default different rank bus delay to 2 CK, @687.5 MHz = 2.91 ns
1290 # Greater of 2 CK or 5 ns
1294 # With Bank Group Arch mode tFAW is 20 ns
1296 activation_limit
= 4
1298 # at 5Gbps, 4:1 WCK to CK ratio required
1299 # 2 data beats per WCK (DDR) -> 8 per CK
1302 # 2 cycles required to send activate command
1303 # 2 command phases can be sent back-to-back or
1304 # with a gap up to tAAD = 8 CK
1305 two_cycle_activate
= True
1308 data_clock_sync
= True
1310 # A single LPDDR5 x16 interface (one command/address bus)
1311 # for a single x16 channel with default timings based on
1312 # initial JEDEC specification
1313 # Starting with 5.5Gbps data rates and 8Gbit die
1314 # Configuring for 16-bank mode with bank-group architecture, burst of 16
1315 class LPDDR5_5500_1x16_BG_BL16(LPDDR5_5500_1x16_BG_BL32
):
1317 # LPDDR5 is a BL16 or BL32 device
1318 # With BG mode, BL16 and BL32 are supported
1319 # Use BL16 for smaller access granularity
1322 # For Bstof16 with BG arch, 2 CK @ 687.5 MHz with 4:1 clock ratio
1324 tBURST_MIN
= '2.91ns'
1325 # For Bstof16 with BG arch, 4 CK @ 687.5 MHz with 4:1 clock ratio
1326 tBURST_MAX
= '5.82ns'
1332 # A single LPDDR5 x16 interface (one command/address bus)
1333 # for a single x16 channel with default timings based on
1334 # initial JEDEC specification
1335 # Starting with 5.5Gbps data rates and 8Gbit die
1336 # Configuring for 8-bank mode, burst of 32
1337 class LPDDR5_5500_1x16_8B_BL32(LPDDR5_5500_1x16_BG_BL32
):
1339 # 4kB page with 8B mode
1340 device_rowbuffer_size
= '4kB'
1342 # LPDDR5 supports configurable bank options
1343 # 8B : BL32, all frequencies
1344 # 16B : BL32 or BL16, <=3.2Gbps
1345 # 16B with Bank Group Arch (4B/BG): BL32 or BL16, >3.2Gbps
1348 bank_groups_per_rank
= 0
1350 # For Bstof32 with 8B mode, 4 CK @ 687.5 MHz with 4:1 clock ratio
1352 tBURST_MIN
= '5.82ns'
1353 tBURST_MAX
= '5.82ns'
1355 # Greater of 4 CK or 12 ns
1358 # Greater of 2 CK or 10 ns
1361 # With 8B mode tFAW is 40 ns
1363 activation_limit
= 4
1365 # Reset BG arch timing for 8B mode
1370 # A single LPDDR5 x16 interface (one command/address bus)
1371 # for a single x16 channel with default timings based on
1372 # initial JEDEC specification
1373 # 6.4Gbps data rates and 8Gbit die
1374 # Configuring for 16-bank mode with bank-group architecture
1375 # burst of 32, which means bursts can be interleaved
1376 class LPDDR5_6400_1x16_BG_BL32(LPDDR5_5500_1x16_BG_BL32
):
1378 # 5.5Gb/s DDR with 4:1 WCK:CK ratio for 687.5 MHz CK
1381 # Base RL is 17 CK @ 800 MHz = 21.25ns
1384 # With BG architecture, burst of 32 transferred in two 16-beat
1385 # sub-bursts, with a 16-beat gap in between.
1386 # Each 16-beat sub-burst is 8 WCK @3.2 GHz or 2 CK @ 800 MHz
1387 # tBURST is the delay to transfer the Bstof32 = 6 CK @ 800 MHz
1389 # can interleave a Bstof32 from another bank group at tBURST_MIN
1390 # 16-beats is 8 WCK @2.3 GHz or 2 CK @ 800 MHz
1391 tBURST_MIN
= '2.5ns'
1392 # tBURST_MAX is the maximum burst delay for same bank group timing
1393 # this is 8 CK @ 800 MHz
1399 # Required RD-to-WR timing is RL+ BL/n + tWCKDQ0/tCK - WL
1400 # tWCKDQ0/tCK will be 1 CK for most cases
1401 # For gem5 RL = WL and BL/n is already accounted for with tBURST
1402 # Result is and additional 1 CK is required
1405 # Default different rank bus delay to 2 CK, @687.5 MHz = 2.5 ns
1411 # 2 command phases can be sent back-to-back or
1412 # with a gap up to tAAD = 8 CK
1415 # A single LPDDR5 x16 interface (one command/address bus)
1416 # for a single x16 channel with default timings based on initial
1417 # JEDEC specifcation
1418 # 6.4Gbps data rates and 8Gbit die
1419 # Configuring for 16-bank mode with bank-group architecture, burst of 16
1420 class LPDDR5_6400_1x16_BG_BL16(LPDDR5_6400_1x16_BG_BL32
):
1422 # LPDDR5 is a BL16 or BL32 device
1423 # With BG mode, BL16 and BL32 are supported
1424 # Use BL16 for smaller access granularity
1427 # For Bstof16 with BG arch, 2 CK @ 800 MHz with 4:1 clock ratio
1429 tBURST_MIN
= '2.5ns'
1430 # For Bstof16 with BG arch, 4 CK @ 800 MHz with 4:1 clock ratio
1437 # A single LPDDR5 x16 interface (one command/address bus)
1438 # for a single x16 channel with default timings based on
1439 # initial JEDEC specification
1440 # 6.4Gbps data rates and 8Gbit die
1441 # Configuring for 8-bank mode, burst of 32
1442 class LPDDR5_6400_1x16_8B_BL32(LPDDR5_6400_1x16_BG_BL32
):
1444 # 4kB page with 8B mode
1445 device_rowbuffer_size
= '4kB'
1447 # LPDDR5 supports configurable bank options
1448 # 8B : BL32, all frequencies
1449 # 16B : BL32 or BL16, <=3.2Gbps
1450 # 16B with Bank Group Arch (4B/BG): BL32 or BL16, >3.2Gbps
1453 bank_groups_per_rank
= 0
1455 # For Bstof32 with 8B mode, 4 CK @ 800 MHz with 4:1 clock ratio
1460 # Greater of 4 CK or 12 ns
1463 # Greater of 2 CK or 10 ns
1466 # With 8B mode tFAW is 40 ns
1468 activation_limit
= 4
1470 # Reset BG arch timing for 8B mode