src/mem/DRAMSim2.py

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  35
  36 from m5.params import *
  37 from m5.objects.AbstractMemory import *
  38
  39 # A wrapper for DRAMSim2 multi-channel memory controller
  40 class DRAMSim2(AbstractMemory):
  41     type = 'DRAMSim2'
  42     cxx_header = "mem/dramsim2.hh"
  43
  44     # A single port for now
  45     port = ResponsePort("This port sends responses and receives requests")
  46
  47     deviceConfigFile = Param.String("ini/DDR3_micron_32M_8B_x8_sg15.ini",
  48                                     "Device configuration file")
  49     systemConfigFile = Param.String("system.ini.example",
  50                                     "Memory organisation configuration file")
  51     filePath = Param.String("ext/dramsim2/DRAMSim2/",
  52                             "Directory to prepend to file names")
  53     traceFile = Param.String("", "Output file for trace generation")
  54     enableDebug = Param.Bool(False, "Enable DRAMSim2 debug output")