src/mem/HMCController.py

   1 # Copyright (c) 2012-2013 ARM Limited
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  13 # Copyright (c) 2015 The University of Bologna
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  38
  39 from m5.params import *
  40 from m5.objects.XBar import *
  41
  42 # References:
  43 # [1] http://www.open-silicon.com/open-silicon-ips/hmc/
  44 # [2] Ahn, J.; Yoo, S.; Choi, K., "Low-Power Hybrid Memory Cubes With Link
  45 #   Power Management and Two-Level Prefetching," TVLSI 2015
  46
  47 # The HMCController class highlights the fact that a component is required
  48 # between host and HMC to convert the host protocol (AXI for example) to the
  49 # serial links protocol. Moreover, this component should have large internal
  50 # queueing to hide the access latency of the HMC.
  51 # Plus, this controller can implement more advanced global scheduling policies
  52 # and can reorder and steer transactions if required. A good example of such
  53 # component is available in [1].
  54 # Also in [2] there is a similar component which is connected to all serial
  55 # links, and it schedules the requests to the ones which are not busy.
  56 # These two references clarify two things:
  57 # 1. The serial links support the same address range and packets can travel
  58 #  over any of them.
  59 # 2. One host can be connected to more than 1 serial link simply to achieve
  60 #  higher bandwidth, and not for any other reason.
  61
  62 # In this model, we have used a round-robin counter, because it is the
  63 # simplest way to schedule packets over the non-busy serial links. However,
  64 # more advanced scheduling algorithms are possible and even host can dedicate
  65 # each serial link to a portion of the address space and interleave packets
  66 # over them. Yet in this model, we have not made any such assumptions on the
  67 # address space.
  68
  69 class HMCController(NoncoherentXBar):
  70         type = 'HMCController'
  71         cxx_header = "mem/hmc_controller.hh"