1 # Copyright (c) 2012-2020 ARM Limited
4 # The license below extends only to copyright in the software and shall
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11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2013 Amin Farmahini-Farahani
14 # Copyright (c) 2015 University of Kaiserslautern
15 # Copyright (c) 2015 The University of Bologna
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41 from m5
.params
import *
42 from m5
.proxy
import *
43 from m5
.objects
.QoSMemCtrl
import *
45 # Enum for memory scheduling algorithms, currently First-Come
46 # First-Served and a First-Row Hit then First-Come First-Served
47 class MemSched(Enum
): vals
= ['fcfs', 'frfcfs']
49 # MemCtrl is a single-channel single-ported Memory controller model
50 # that aims to model the most important system-level performance
51 # effects of a memory controller, interfacing with media specific
53 class MemCtrl(QoSMemCtrl
):
55 cxx_header
= "mem/mem_ctrl.hh"
57 # single-ported on the system interface side, instantiate with a
58 # bus in front of the controller for multiple ports
59 port
= ResponsePort("This port responds to memory requests")
61 # Interface to volatile, DRAM media
62 dram
= Param
.DRAMInterface(NULL
, "DRAM interface")
64 # Interface to non-volatile media
65 nvm
= Param
.NVMInterface(NULL
, "NVM interface")
67 # read and write buffer depths are set in the interface
68 # the controller will read these values when instantiated
70 # threshold in percent for when to forcefully trigger writes and
71 # start emptying the write buffer
72 write_high_thresh_perc
= Param
.Percent(85, "Threshold to force writes")
74 # threshold in percentage for when to start writes if the read
76 write_low_thresh_perc
= Param
.Percent(50, "Threshold to start writes")
78 # minimum write bursts to schedule before switching back to reads
79 min_writes_per_switch
= Param
.Unsigned(16, "Minimum write bursts before "
82 # scheduler, address map and page policy
83 mem_sched_policy
= Param
.MemSched('frfcfs', "Memory scheduling policy")
85 # pipeline latency of the controller and PHY, split into a
86 # frontend part and a backend part, with reads and writes serviced
87 # by the queues only seeing the frontend contribution, and reads
88 # serviced by the memory seeing the sum of the two
89 static_frontend_latency
= Param
.Latency("10ns", "Static frontend latency")
90 static_backend_latency
= Param
.Latency("10ns", "Static backend latency")
92 command_window
= Param
.Latency("10ns", "Static backend latency")