src/mem/MemCtrl.py

   1 # Copyright (c) 2012-2020 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2013 Amin Farmahini-Farahani
  14 # Copyright (c) 2015 University of Kaiserslautern
  15 # Copyright (c) 2015 The University of Bologna
  16 # All rights reserved.
  17 #
  18 # Redistribution and use in source and binary forms, with or without
  19 # modification, are permitted provided that the following conditions are
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  23 # notice, this list of conditions and the following disclaimer in the
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  25 # neither the name of the copyright holders nor the names of its
  26 # contributors may be used to endorse or promote products derived from
  27 # this software without specific prior written permission.
  28 #
  29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  40
  41 from m5.params import *
  42 from m5.proxy import *
  43 from m5.objects.QoSMemCtrl import *
  44
  45 # Enum for memory scheduling algorithms, currently First-Come
  46 # First-Served and a First-Row Hit then First-Come First-Served
  47 class MemSched(Enum): vals = ['fcfs', 'frfcfs']
  48
  49 # MemCtrl is a single-channel single-ported Memory controller model
  50 # that aims to model the most important system-level performance
  51 # effects of a memory controller, interfacing with media specific
  52 # interfaces
  53 class MemCtrl(QoSMemCtrl):
  54     type = 'MemCtrl'
  55     cxx_header = "mem/mem_ctrl.hh"
  56
  57     # single-ported on the system interface side, instantiate with a
  58     # bus in front of the controller for multiple ports
  59     port = ResponsePort("This port responds to memory requests")
  60
  61     # Interface to volatile, DRAM media
  62     dram = Param.DRAMInterface(NULL, "DRAM interface")
  63
  64     # Interface to non-volatile media
  65     nvm = Param.NVMInterface(NULL, "NVM interface")
  66
  67     # read and write buffer depths are set in the interface
  68     # the controller will read these values when instantiated
  69
  70     # threshold in percent for when to forcefully trigger writes and
  71     # start emptying the write buffer
  72     write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
  73
  74     # threshold in percentage for when to start writes if the read
  75     # queue is empty
  76     write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
  77
  78     # minimum write bursts to schedule before switching back to reads
  79     min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
  80                                            "switching to reads")
  81
  82     # scheduler, address map and page policy
  83     mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
  84
  85     # pipeline latency of the controller and PHY, split into a
  86     # frontend part and a backend part, with reads and writes serviced
  87     # by the queues only seeing the frontend contribution, and reads
  88     # serviced by the memory seeing the sum of the two
  89     static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
  90     static_backend_latency = Param.Latency("10ns", "Static backend latency")
  91
  92     command_window = Param.Latency("10ns", "Static backend latency")