1 # Copyright (c) 2012-2020 ARM Limited
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13 # Copyright (c) 2013 Amin Farmahini-Farahani
14 # Copyright (c) 2015 University of Kaiserslautern
15 # Copyright (c) 2015 The University of Bologna
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41 from m5
.params
import *
42 from m5
.proxy
import *
44 from m5
.objects
.AbstractMemory
import AbstractMemory
46 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
47 # channel, rank, bank, row and column, respectively, and going from
48 # MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
49 # suitable for an open-page policy, optimising for sequential accesses
50 # hitting in the open row. For a closed-page policy, RoCoRaBaCh
51 # maximises parallelism.
52 class AddrMap(Enum
): vals
= ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
54 class MemInterface(AbstractMemory
):
57 cxx_header
= "mem/mem_interface.hh"
59 # Allow the interface to set required controller buffer sizes
60 # each entry corresponds to a burst for the specific memory channel
61 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
62 # the cacheline size or request/packet size
63 write_buffer_size
= Param
.Unsigned(64, "Number of write queue entries")
64 read_buffer_size
= Param
.Unsigned(32, "Number of read queue entries")
66 # scheduler, address map
67 addr_mapping
= Param
.AddrMap('RoRaBaCoCh', "Address mapping policy")
69 # size of memory device in Bytes
70 device_size
= Param
.MemorySize("Size of memory device")
71 # the physical organisation of the memory
72 device_bus_width
= Param
.Unsigned("data bus width in bits for each "\
74 burst_length
= Param
.Unsigned("Burst lenght (BL) in beats")
75 device_rowbuffer_size
= Param
.MemorySize("Page (row buffer) size per "\
77 devices_per_rank
= Param
.Unsigned("Number of devices/chips per rank")
78 ranks_per_channel
= Param
.Unsigned("Number of ranks per channel")
79 banks_per_rank
= Param
.Unsigned("Number of banks per rank")
81 # timing behaviour and constraints - all in nanoseconds
83 # the base clock period of the memory
84 tCK
= Param
.Latency("Clock period")
86 # time to complete a burst transfer, typically the burst length
87 # divided by two due to the DDR bus, but by making it a parameter
88 # it is easier to also evaluate SDR memories like WideIO and new
89 # interfaces, emerging technologies.
90 # This parameter has to account for burst length.
91 # Read/Write requests with data size larger than one full burst are broken
92 # down into multiple requests in the controller
93 tBURST
= Param
.Latency("Burst duration "
94 "(typically burst length / 2 cycles)")
96 # write-to-read, same rank turnaround penalty
97 tWTR
= Param
.Latency("Write to read, same rank switching time")
99 # read-to-write, same rank turnaround penalty
100 tRTW
= Param
.Latency("Read to write, same rank switching time")
102 # rank-to-rank bus delay penalty
103 # this does not correlate to a memory timing parameter and encompasses:
104 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
105 # different rank bus delay
106 tCS
= Param
.Latency("Rank to rank switching time")