src/mem/NVMInterface.py

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  35
  36 from m5.params import *
  37 from m5.proxy import *
  38 from m5.objects.MemInterface import MemInterface
  39 from m5.objects.DRAMInterface import AddrMap
  40
  41 # The following interface aims to model byte-addressable NVM
  42 # The most important system-level performance effects of a NVM
  43 # are modeled without getting into too much detail of the media itself.
  44 class NVMInterface(MemInterface):
  45     type = 'NVMInterface'
  46     cxx_header = "mem/mem_interface.hh"
  47
  48     # NVM DIMM could have write buffer to offload writes
  49     # define buffer depth, which will limit the number of pending writes
  50     max_pending_writes = Param.Unsigned("1", "Max pending write commands")
  51
  52     # NVM DIMM could have buffer to offload read commands
  53     # define buffer depth, which will limit the number of pending reads
  54     max_pending_reads = Param.Unsigned("1", "Max pending read commands")
  55
  56     # timing behaviour and constraints - all in nanoseconds
  57
  58     # define average latency for NVM media.  Latency defined uniquely
  59     # for read and writes as the media is typically not symmetric
  60     tREAD = Param.Latency("100ns", "Average NVM read latency")
  61     tWRITE = Param.Latency("200ns", "Average NVM write latency")
  62     tSEND = Param.Latency("15ns", "Access latency")
  63
  64     two_cycle_rdwr = Param.Bool(False,
  65                      "Two cycles required to send read and write commands")
  66
  67 # NVM delays and device architecture defined to mimic PCM like memory.
  68 # Can be configured with DDR4_2400 sharing the channel
  69 class NVM_2400_1x64(NVMInterface):
  70     write_buffer_size = 128
  71     read_buffer_size = 64
  72
  73     max_pending_writes = 128
  74     max_pending_reads = 64
  75
  76     device_rowbuffer_size = '256B'
  77
  78     # 8X capacity compared to DDR4 x4 DIMM with 8Gb devices
  79     device_size = '512GiB'
  80     # Mimic 64-bit media agnostic DIMM interface
  81     device_bus_width = 64
  82     devices_per_rank = 1
  83     ranks_per_channel = 1
  84     banks_per_rank = 16
  85
  86     burst_length = 8
  87
  88     two_cycle_rdwr = True
  89
  90     # 1200 MHz
  91     tCK = '0.833ns'
  92
  93     tREAD = '150ns'
  94     tWRITE = '500ns';
  95     tSEND = '14.16ns';
  96     tBURST = '3.332ns';
  97
  98     # Default all bus turnaround and rank bus delay to 2 cycles
  99     # With DDR data bus, clock = 1200 MHz = 1.666 ns
 100     tWTR = '1.666ns';
 101     tRTW = '1.666ns';
 102     tCS = '1.666ns'
 103