src/mem/PhysicalMemory.py

   1 # Copyright (c) 2005-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
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   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Nathan Binkert
  28
  29 from m5.params import *
  30 from m5.proxy import *
  31 from MemObject import *
  32
  33 class PhysicalMemory(MemObject):
  34     type = 'PhysicalMemory'
  35     port = VectorPort("the access port")
  36     range = Param.AddrRange(AddrRange('128MB'), "Device Address")
  37     file = Param.String('', "memory mapped file")
  38     latency = Param.Latency('1t', "latency of an access")
  39     zero = Param.Bool(False, "zero initialize memory")
  40
  41 class DRAMMemory(PhysicalMemory):
  42     type = 'DRAMMemory'
  43     # Many of these should be observed from the configuration
  44     cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed")
  45     mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)")
  46     mem_actpolicy = Param.String("open", "Open/Close policy")
  47     memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
  48     bus_width = Param.Int(16, "")
  49     act_lat = Param.Int(2, "RAS to CAS delay")
  50     cas_lat = Param.Int(1, "CAS delay")
  51     war_lat = Param.Int(2, "write after read delay")
  52     pre_lat = Param.Int(2, "precharge delay")
  53     dpl_lat = Param.Int(2, "data in to precharge delay")
  54     trc_lat = Param.Int(6, "row cycle delay")
  55     num_banks = Param.Int(4, "Number of Banks")
  56     num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")
  57