1 # Copyright (c) 2005-2008 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Nathan Binkert
29 from m5
.params
import *
30 from m5
.proxy
import *
31 from MemObject
import *
33 class PhysicalMemory(MemObject
):
34 type = 'PhysicalMemory'
35 port
= VectorPort("the access port")
36 range = Param
.AddrRange(AddrRange('128MB'), "Device Address")
37 file = Param
.String('', "memory mapped file")
38 latency
= Param
.Latency('30ns', "latency of an access")
39 latency_var
= Param
.Latency('0ns', "access variablity")
40 zero
= Param
.Bool(False, "zero initialize memory")
41 null
= Param
.Bool(False, "do not store data, always return zero")
43 class DRAMMemory(PhysicalMemory
):
45 # Many of these should be observed from the configuration
46 cpu_ratio
= Param
.Int(5,"ratio between CPU speed and memory bus speed")
47 mem_type
= Param
.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)")
48 mem_actpolicy
= Param
.String("open", "Open/Close policy")
49 memctrladdr_type
= Param
.String("interleaved", "Mapping interleaved or direct")
50 bus_width
= Param
.Int(16, "")
51 act_lat
= Param
.Latency("2ns", "RAS to CAS delay")
52 cas_lat
= Param
.Latency("1ns", "CAS delay")
53 war_lat
= Param
.Latency("2ns", "write after read delay")
54 pre_lat
= Param
.Latency("2ns", "precharge delay")
55 dpl_lat
= Param
.Latency("2ns", "data in to precharge delay")
56 trc_lat
= Param
.Latency("6ns", "row cycle delay")
57 num_banks
= Param
.Int(4, "Number of Banks")
58 num_cpus
= Param
.Int(4, "Number of CPUs connected to DRAM")