mem: Remove the unused asid field from the CacheBlk class
[gem5.git] / src / mem / SConscript
1 # -*- mode:python -*-
2
3 # Copyright (c) 2006 The Regents of The University of Michigan
4 # All rights reserved.
5 #
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
16 #
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #
29 # Authors: Nathan Binkert
30
31 Import('*')
32
33 SimObject('CommMonitor.py')
34 Source('comm_monitor.cc')
35
36 SimObject('AbstractMemory.py')
37 SimObject('AddrMapper.py')
38 SimObject('Bridge.py')
39 SimObject('DRAMCtrl.py')
40 SimObject('ExternalMaster.py')
41 SimObject('ExternalSlave.py')
42 SimObject('MemObject.py')
43 SimObject('SimpleMemory.py')
44 SimObject('XBar.py')
45 SimObject('HMCController.py')
46 SimObject('SerialLink.py')
47
48 Source('abstract_mem.cc')
49 Source('addr_mapper.cc')
50 Source('bridge.cc')
51 Source('coherent_xbar.cc')
52 Source('drampower.cc')
53 Source('dram_ctrl.cc')
54 Source('external_master.cc')
55 Source('external_slave.cc')
56 Source('mem_object.cc')
57 Source('mport.cc')
58 Source('noncoherent_xbar.cc')
59 Source('packet.cc')
60 Source('port.cc')
61 Source('packet_queue.cc')
62 Source('port_proxy.cc')
63 Source('physical.cc')
64 Source('simple_mem.cc')
65 Source('snoop_filter.cc')
66 Source('stack_dist_calc.cc')
67 Source('tport.cc')
68 Source('xbar.cc')
69 Source('hmc_controller.cc')
70 Source('serial_link.cc')
71
72 if env['TARGET_ISA'] != 'null':
73 Source('fs_translating_port_proxy.cc')
74 Source('se_translating_port_proxy.cc')
75 Source('page_table.cc')
76 if env['TARGET_ISA'] == 'x86':
77 Source('multi_level_page_table.cc')
78
79 if env['HAVE_DRAMSIM']:
80 SimObject('DRAMSim2.py')
81 Source('dramsim2_wrapper.cc')
82 Source('dramsim2.cc')
83
84 SimObject('MemChecker.py')
85 Source('mem_checker.cc')
86 Source('mem_checker_monitor.cc')
87
88 DebugFlag('AddrRanges')
89 DebugFlag('BaseXBar')
90 DebugFlag('CoherentXBar')
91 DebugFlag('NoncoherentXBar')
92 DebugFlag('SnoopFilter')
93 CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
94 'SnoopFilter'])
95
96 DebugFlag('Bridge')
97 DebugFlag('CommMonitor')
98 DebugFlag('DRAM')
99 DebugFlag('DRAMPower')
100 DebugFlag('DRAMState')
101 DebugFlag('ExternalPort')
102 DebugFlag('LLSC')
103 DebugFlag('MMU')
104 DebugFlag('MemoryAccess')
105 DebugFlag('PacketQueue')
106 DebugFlag('StackDist')
107 DebugFlag("DRAMSim2")
108 DebugFlag('HMCController')
109 DebugFlag('SerialLink')
110
111 DebugFlag("MemChecker")
112 DebugFlag("MemCheckerMonitor")