src/mem/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2006 The Regents of The University of Michigan
   4 # All rights reserved.
   5 #
   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are
   8 # met: redistributions of source code must retain the above copyright
   9 # notice, this list of conditions and the following disclaimer;
  10 # redistributions in binary form must reproduce the above copyright
  11 # notice, this list of conditions and the following disclaimer in the
  12 # documentation and/or other materials provided with the distribution;
  13 # neither the name of the copyright holders nor the names of its
  14 # contributors may be used to endorse or promote products derived from
  15 # this software without specific prior written permission.
  16 #
  17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 #
  29 # Authors: Nathan Binkert
  30
  31 Import('*')
  32
  33 # Only build the communication if we have support for protobuf as the
  34 # tracing relies on it
  35 if env['HAVE_PROTOBUF']:
  36     SimObject('CommMonitor.py')
  37     Source('comm_monitor.cc')
  38
  39 SimObject('AbstractMemory.py')
  40 SimObject('AddrMapper.py')
  41 SimObject('Bridge.py')
  42 SimObject('DRAMCtrl.py')
  43 SimObject('MemObject.py')
  44 SimObject('SimpleMemory.py')
  45 SimObject('XBar.py')
  46
  47 Source('abstract_mem.cc')
  48 Source('addr_mapper.cc')
  49 Source('bridge.cc')
  50 Source('coherent_xbar.cc')
  51 Source('dram_ctrl.cc')
  52 Source('mem_object.cc')
  53 Source('mport.cc')
  54 Source('noncoherent_xbar.cc')
  55 Source('packet.cc')
  56 Source('port.cc')
  57 Source('packet_queue.cc')
  58 Source('port_proxy.cc')
  59 Source('physical.cc')
  60 Source('simple_mem.cc')
  61 Source('snoop_filter.cc')
  62 Source('tport.cc')
  63 Source('xbar.cc')
  64
  65 if env['TARGET_ISA'] != 'null':
  66     Source('fs_translating_port_proxy.cc')
  67     Source('se_translating_port_proxy.cc')
  68     Source('page_table.cc')
  69 if env['TARGET_ISA'] == 'x86':
  70     Source('multi_level_page_table.cc')
  71
  72 if env['HAVE_DRAMSIM']:
  73     SimObject('DRAMSim2.py')
  74     Source('dramsim2_wrapper.cc')
  75     Source('dramsim2.cc')
  76
  77 DebugFlag('AddrRanges')
  78 DebugFlag('BaseXBar')
  79 DebugFlag('CoherentXBar')
  80 DebugFlag('NoncoherentXBar')
  81 DebugFlag('SnoopFilter')
  82 CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
  83                       'SnoopFilter'])
  84
  85 DebugFlag('Bridge')
  86 DebugFlag('CommMonitor')
  87 DebugFlag('DRAM')
  88 DebugFlag('DRAMPower')
  89 DebugFlag('DRAMState')
  90 DebugFlag('LLSC')
  91 DebugFlag('MMU')
  92 DebugFlag('MemoryAccess')
  93 DebugFlag('PacketQueue')
  94
  95 DebugFlag("DRAMSim2")