3 # Copyright (c) 2006 The Regents of The University of Michigan
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 # Authors: Nathan Binkert
33 SimObject('AddrMapper.py')
34 SimObject('Bridge.py')
36 SimObject('CommMonitor.py')
37 SimObject('MemObject.py')
39 Source('addr_mapper.cc')
42 Source('coherent_bus.cc')
43 Source('comm_monitor.cc')
44 Source('mem_object.cc')
46 Source('noncoherent_bus.cc')
49 Source('packet_queue.cc')
51 Source('port_proxy.cc')
52 Source('fs_translating_port_proxy.cc')
53 Source('se_translating_port_proxy.cc')
55 if env['TARGET_ISA'] != 'no':
56 SimObject('AbstractMemory.py')
57 SimObject('SimpleMemory.py')
58 SimObject('SimpleDRAM.py')
59 Source('abstract_mem.cc')
60 Source('simple_mem.cc')
61 Source('page_table.cc')
63 Source('simple_dram.cc')
66 DebugFlag('BusAddrRanges')
67 DebugFlag('CoherentBus')
68 DebugFlag('NoncoherentBus')
69 CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
73 DebugFlag('CommMonitor')
78 DebugFlag('MemoryAccess')
79 DebugFlag('PacketQueue')
81 DebugFlag('ProtocolTrace')
82 DebugFlag('RubyCache')
83 DebugFlag('RubyCacheTrace')
85 DebugFlag('RubyGenerated')
86 DebugFlag('RubyMemory')
87 DebugFlag('RubyNetwork')
89 DebugFlag('RubyPrefetcher')
90 DebugFlag('RubyQueue')
91 DebugFlag('RubySequencer')
92 DebugFlag('RubySlicc')
93 DebugFlag('RubySystem')
94 DebugFlag('RubyTester')
95 DebugFlag('RubyStats')
96 DebugFlag('RubyResourceStalls')
98 CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
99 'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
100 'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace',