src/mem/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2006 The Regents of The University of Michigan
   4 # All rights reserved.
   5 #
   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are
   8 # met: redistributions of source code must retain the above copyright
   9 # notice, this list of conditions and the following disclaimer;
  10 # redistributions in binary form must reproduce the above copyright
  11 # notice, this list of conditions and the following disclaimer in the
  12 # documentation and/or other materials provided with the distribution;
  13 # neither the name of the copyright holders nor the names of its
  14 # contributors may be used to endorse or promote products derived from
  15 # this software without specific prior written permission.
  16 #
  17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 #
  29 # Authors: Nathan Binkert
  30
  31 Import('*')
  32
  33 SimObject('Bridge.py')
  34 SimObject('Bus.py')
  35 SimObject('MemObject.py')
  36
  37 Source('bridge.cc')
  38 Source('bus.cc')
  39 Source('mem_object.cc')
  40 Source('packet.cc')
  41 Source('port.cc')
  42 Source('tport.cc')
  43 Source('mport.cc')
  44
  45 if env['TARGET_ISA'] != 'no':
  46     SimObject('PhysicalMemory.py')
  47     Source('dram.cc')
  48     Source('physical.cc')
  49
  50 if env['FULL_SYSTEM']:
  51     Source('vport.cc')
  52 elif env['TARGET_ISA'] != 'no':
  53     Source('page_table.cc')
  54     Source('translating_port.cc')
  55
  56 TraceFlag('Bus')
  57 TraceFlag('BusAddrRanges')
  58 TraceFlag('BusBridge')
  59 TraceFlag('LLSC')
  60 TraceFlag('MMU')
  61 TraceFlag('MemoryAccess')
  62
  63 TraceFlag('ProtocolTrace')
  64 TraceFlag('RubyCache')
  65 TraceFlag('RubyDma')
  66 TraceFlag('RubyGenerated')
  67 TraceFlag('RubyMemory')
  68 TraceFlag('RubyNetwork')
  69 TraceFlag('RubyPort')
  70 TraceFlag('RubyQueue')
  71 TraceFlag('RubySlicc')
  72 TraceFlag('RubyStorebuffer')
  73 TraceFlag('RubyTester')
  74
  75 CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
  76     'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache',
  77     'RubyMemory', 'RubyDma', 'RubyPort'])