ca89418b54ebd8d3a0bc8619ef2d58221755f608
[gem5.git] / src / mem / SConscript
1 # -*- mode:python -*-
2
3 # Copyright (c) 2006 The Regents of The University of Michigan
4 # All rights reserved.
5 #
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
16 #
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #
29 # Authors: Nathan Binkert
30
31 Import('*')
32
33 # Only build the communication if we have support for protobuf as the
34 # tracing relies on it
35 if env['HAVE_PROTOBUF']:
36 SimObject('CommMonitor.py')
37 Source('comm_monitor.cc')
38
39 SimObject('AddrMapper.py')
40 SimObject('Bridge.py')
41 SimObject('Bus.py')
42 SimObject('MemObject.py')
43
44 Source('addr_mapper.cc')
45 Source('bridge.cc')
46 Source('bus.cc')
47 Source('coherent_bus.cc')
48 Source('mem_object.cc')
49 Source('mport.cc')
50 Source('noncoherent_bus.cc')
51 Source('packet.cc')
52 Source('port.cc')
53 Source('packet_queue.cc')
54 Source('tport.cc')
55 Source('port_proxy.cc')
56 Source('fs_translating_port_proxy.cc')
57 Source('se_translating_port_proxy.cc')
58
59 if env['TARGET_ISA'] != 'no':
60 SimObject('AbstractMemory.py')
61 SimObject('SimpleMemory.py')
62 SimObject('SimpleDRAM.py')
63 Source('abstract_mem.cc')
64 Source('simple_mem.cc')
65 Source('page_table.cc')
66 Source('physical.cc')
67 Source('simple_dram.cc')
68
69 DebugFlag('BaseBus')
70 DebugFlag('BusAddrRanges')
71 DebugFlag('CoherentBus')
72 DebugFlag('NoncoherentBus')
73 CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
74 'NoncoherentBus'])
75
76 DebugFlag('Bridge')
77 DebugFlag('CommMonitor')
78 DebugFlag('DRAM')
79 DebugFlag('DRAMWR')
80 DebugFlag('LLSC')
81 DebugFlag('MMU')
82 DebugFlag('MemoryAccess')
83 DebugFlag('PacketQueue')
84
85 DebugFlag('ProtocolTrace')
86 DebugFlag('RubyCache')
87 DebugFlag('RubyCacheTrace')
88 DebugFlag('RubyDma')
89 DebugFlag('RubyGenerated')
90 DebugFlag('RubyMemory')
91 DebugFlag('RubyNetwork')
92 DebugFlag('RubyPort')
93 DebugFlag('RubyPrefetcher')
94 DebugFlag('RubyQueue')
95 DebugFlag('RubySequencer')
96 DebugFlag('RubySlicc')
97 DebugFlag('RubySystem')
98 DebugFlag('RubyTester')
99 DebugFlag('RubyStats')
100 DebugFlag('RubyResourceStalls')
101
102 CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
103 'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
104 'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace',
105 'RubyPrefetcher'])