src/mem/SConscript

   1 # -*- mode:python -*-
   2 #
   3 # Copyright (c) 2018-2020 ARM Limited
   4 # All rights reserved
   5 #
   6 # The license below extends only to copyright in the software and shall
   7 # not be construed as granting a license to any other intellectual
   8 # property including but not limited to intellectual property relating
   9 # to a hardware implementation of the functionality of the software
  10 # licensed hereunder.  You may use the software subject to the license
  11 # terms below provided that you ensure that this notice is replicated
  12 # unmodified and in its entirety in all distributions of the software,
  13 # modified or unmodified, in source code or in binary form.
  14 #
  15 # Copyright (c) 2006 The Regents of The University of Michigan
  16 # All rights reserved.
  17 #
  18 # Redistribution and use in source and binary forms, with or without
  19 # modification, are permitted provided that the following conditions are
  20 # met: redistributions of source code must retain the above copyright
  21 # notice, this list of conditions and the following disclaimer;
  22 # redistributions in binary form must reproduce the above copyright
  23 # notice, this list of conditions and the following disclaimer in the
  24 # documentation and/or other materials provided with the distribution;
  25 # neither the name of the copyright holders nor the names of its
  26 # contributors may be used to endorse or promote products derived from
  27 # this software without specific prior written permission.
  28 #
  29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40
  41 Import('*')
  42
  43 SimObject('CommMonitor.py')
  44 Source('comm_monitor.cc')
  45
  46 SimObject('AbstractMemory.py')
  47 SimObject('AddrMapper.py')
  48 SimObject('Bridge.py')
  49 SimObject('MemCtrl.py')
  50 SimObject('MemInterface.py')
  51 SimObject('DRAMInterface.py')
  52 SimObject('NVMInterface.py')
  53 SimObject('ExternalMaster.py')
  54 SimObject('ExternalSlave.py')
  55 SimObject('MemObject.py')
  56 SimObject('SimpleMemory.py')
  57 SimObject('XBar.py')
  58 SimObject('HMCController.py')
  59 SimObject('SerialLink.py')
  60 SimObject('MemDelay.py')
  61
  62 Source('abstract_mem.cc')
  63 Source('addr_mapper.cc')
  64 Source('bridge.cc')
  65 Source('coherent_xbar.cc')
  66 Source('drampower.cc')
  67 Source('external_master.cc')
  68 Source('external_slave.cc')
  69 Source('mem_ctrl.cc')
  70 Source('mem_interface.cc')
  71 Source('noncoherent_xbar.cc')
  72 Source('packet.cc')
  73 Source('port.cc')
  74 Source('packet_queue.cc')
  75 Source('port_proxy.cc')
  76 Source('physical.cc')
  77 Source('simple_mem.cc')
  78 Source('snoop_filter.cc')
  79 Source('stack_dist_calc.cc')
  80 Source('token_port.cc')
  81 Source('tport.cc')
  82 Source('xbar.cc')
  83 Source('hmc_controller.cc')
  84 Source('htm.cc')
  85 Source('serial_link.cc')
  86 Source('mem_delay.cc')
  87
  88 if env['TARGET_ISA'] != 'null':
  89     Source('translating_port_proxy.cc')
  90     Source('se_translating_port_proxy.cc')
  91     Source('page_table.cc')
  92
  93 if env['HAVE_DRAMSIM']:
  94     SimObject('DRAMSim2.py')
  95     Source('dramsim2_wrapper.cc')
  96     Source('dramsim2.cc')
  97
  98 if env['HAVE_DRAMSIM3']:
  99     SimObject('DRAMsim3.py')
 100     Source('dramsim3_wrapper.cc')
 101     Source('dramsim3.cc')
 102
 103 SimObject('MemChecker.py')
 104 Source('mem_checker.cc')
 105 Source('mem_checker_monitor.cc')
 106
 107 DebugFlag('AddrRanges')
 108 DebugFlag('BaseXBar')
 109 DebugFlag('CoherentXBar')
 110 DebugFlag('NoncoherentXBar')
 111 DebugFlag('SnoopFilter')
 112 CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
 113                       'SnoopFilter'])
 114
 115 DebugFlag('Bridge')
 116 DebugFlag('CommMonitor')
 117 DebugFlag('DRAM')
 118 DebugFlag('DRAMPower')
 119 DebugFlag('DRAMState')
 120 DebugFlag('NVM')
 121 DebugFlag('ExternalPort')
 122 DebugFlag('HtmMem', 'Hardware Transactional Memory (Mem side)')
 123 DebugFlag('LLSC')
 124 DebugFlag('MemCtrl')
 125 DebugFlag('MMU')
 126 DebugFlag('MemoryAccess')
 127 DebugFlag('PacketQueue')
 128 DebugFlag('StackDist')
 129 DebugFlag("DRAMSim2")
 130 DebugFlag("DRAMsim3")
 131 DebugFlag('HMCController')
 132 DebugFlag('SerialLink')
 133 DebugFlag('TokenPort')
 134
 135 DebugFlag("MemChecker")
 136 DebugFlag("MemCheckerMonitor")
 137 DebugFlag("QOS")