3 # Copyright (c) 2018 ARM Limited
6 # The license below extends only to copyright in the software and shall
7 # not be construed as granting a license to any other intellectual
8 # property including but not limited to intellectual property relating
9 # to a hardware implementation of the functionality of the software
10 # licensed hereunder. You may use the software subject to the license
11 # terms below provided that you ensure that this notice is replicated
12 # unmodified and in its entirety in all distributions of the software,
13 # modified or unmodified, in source code or in binary form.
15 # Copyright (c) 2006 The Regents of The University of Michigan
16 # All rights reserved.
18 # Redistribution and use in source and binary forms, with or without
19 # modification, are permitted provided that the following conditions are
20 # met: redistributions of source code must retain the above copyright
21 # notice, this list of conditions and the following disclaimer;
22 # redistributions in binary form must reproduce the above copyright
23 # notice, this list of conditions and the following disclaimer in the
24 # documentation and/or other materials provided with the distribution;
25 # neither the name of the copyright holders nor the names of its
26 # contributors may be used to endorse or promote products derived from
27 # this software without specific prior written permission.
29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 SimObject('CommMonitor.py')
44 Source('comm_monitor.cc')
46 SimObject('AbstractMemory.py')
47 SimObject('AddrMapper.py')
48 SimObject('Bridge.py')
49 SimObject('DRAMCtrl.py')
50 SimObject('ExternalMaster.py')
51 SimObject('ExternalSlave.py')
52 SimObject('MemObject.py')
53 SimObject('SimpleMemory.py')
55 SimObject('HMCController.py')
56 SimObject('SerialLink.py')
57 SimObject('MemDelay.py')
59 Source('abstract_mem.cc')
60 Source('addr_mapper.cc')
62 Source('coherent_xbar.cc')
63 Source('drampower.cc')
64 Source('dram_ctrl.cc')
65 Source('external_master.cc')
66 Source('external_slave.cc')
67 Source('noncoherent_xbar.cc')
70 Source('packet_queue.cc')
71 Source('port_proxy.cc')
73 Source('secure_port_proxy.cc')
74 Source('simple_mem.cc')
75 Source('snoop_filter.cc')
76 Source('stack_dist_calc.cc')
79 Source('hmc_controller.cc')
80 Source('serial_link.cc')
81 Source('mem_delay.cc')
83 if env['TARGET_ISA'] != 'null':
84 Source('fs_translating_port_proxy.cc')
85 Source('se_translating_port_proxy.cc')
86 Source('page_table.cc')
88 if env['HAVE_DRAMSIM']:
89 SimObject('DRAMSim2.py')
90 Source('dramsim2_wrapper.cc')
93 SimObject('MemChecker.py')
94 Source('mem_checker.cc')
95 Source('mem_checker_monitor.cc')
97 DebugFlag('AddrRanges')
99 DebugFlag('CoherentXBar')
100 DebugFlag('NoncoherentXBar')
101 DebugFlag('SnoopFilter')
102 CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
106 DebugFlag('CommMonitor')
108 DebugFlag('DRAMPower')
109 DebugFlag('DRAMState')
110 DebugFlag('ExternalPort')
113 DebugFlag('MemoryAccess')
114 DebugFlag('PacketQueue')
115 DebugFlag('StackDist')
116 DebugFlag("DRAMSim2")
117 DebugFlag('HMCController')
118 DebugFlag('SerialLink')
120 DebugFlag("MemChecker")
121 DebugFlag("MemCheckerMonitor")