mem: Add a wrapped DRAMSim2 memory controller
[gem5.git] / src / mem / SConscript
1 # -*- mode:python -*-
2
3 # Copyright (c) 2006 The Regents of The University of Michigan
4 # All rights reserved.
5 #
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
16 #
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #
29 # Authors: Nathan Binkert
30
31 Import('*')
32
33 # Only build the communication if we have support for protobuf as the
34 # tracing relies on it
35 if env['HAVE_PROTOBUF']:
36 SimObject('CommMonitor.py')
37 Source('comm_monitor.cc')
38
39 SimObject('AbstractMemory.py')
40 SimObject('AddrMapper.py')
41 SimObject('Bridge.py')
42 SimObject('Bus.py')
43 SimObject('MemObject.py')
44 SimObject('SimpleMemory.py')
45 SimObject('SimpleDRAM.py')
46
47 Source('abstract_mem.cc')
48 Source('addr_mapper.cc')
49 Source('bridge.cc')
50 Source('bus.cc')
51 Source('coherent_bus.cc')
52 Source('mem_object.cc')
53 Source('mport.cc')
54 Source('noncoherent_bus.cc')
55 Source('packet.cc')
56 Source('port.cc')
57 Source('packet_queue.cc')
58 Source('tport.cc')
59 Source('port_proxy.cc')
60 Source('simple_mem.cc')
61 Source('physical.cc')
62 Source('simple_dram.cc')
63
64 if env['TARGET_ISA'] != 'null':
65 Source('fs_translating_port_proxy.cc')
66 Source('se_translating_port_proxy.cc')
67 Source('page_table.cc')
68
69 if env['HAVE_DRAMSIM']:
70 SimObject('DRAMSim2.py')
71 Source('dramsim2_wrapper.cc')
72 Source('dramsim2.cc')
73
74 DebugFlag('BaseBus')
75 DebugFlag('BusAddrRanges')
76 DebugFlag('CoherentBus')
77 DebugFlag('NoncoherentBus')
78 CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
79 'NoncoherentBus'])
80
81 DebugFlag('Bridge')
82 DebugFlag('CommMonitor')
83 DebugFlag('DRAM')
84 DebugFlag('LLSC')
85 DebugFlag('MMU')
86 DebugFlag('MemoryAccess')
87 DebugFlag('PacketQueue')
88
89 DebugFlag("DRAMSim2")
90
91 DebugFlag('ProtocolTrace')
92 DebugFlag('RubyCache')
93 DebugFlag('RubyCacheTrace')
94 DebugFlag('RubyDma')
95 DebugFlag('RubyGenerated')
96 DebugFlag('RubyMemory')
97 DebugFlag('RubyNetwork')
98 DebugFlag('RubyPort')
99 DebugFlag('RubyPrefetcher')
100 DebugFlag('RubyQueue')
101 DebugFlag('RubySequencer')
102 DebugFlag('RubySlicc')
103 DebugFlag('RubySystem')
104 DebugFlag('RubyTester')
105 DebugFlag('RubyStats')
106 DebugFlag('RubyResourceStalls')
107
108 CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
109 'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
110 'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace',
111 'RubyPrefetcher'])