src/mem/SerialLink.py

   1 # Copyright (c) 2012-2013 ARM Limited
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  13 # Copyright (c) 2006-2007 The Regents of The University of Michigan
  14 # Copyright (c) 2015 The University of Bologna
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  39 #
  40 # Authors: Ali Saidi
  41 #          Andreas Hansson
  42 #          Erfan Azarkhish
  43
  44 from m5.params import *
  45 from m5.objects.ClockedObject import ClockedObject
  46
  47 # SerialLink is a simple variation of the Bridge class, with the ability to
  48 # account for the latency of packet serialization.
  49
  50 class SerialLink(ClockedObject):
  51     type = 'SerialLink'
  52     cxx_header = "mem/serial_link.hh"
  53     slave = SlavePort('Slave port')
  54     master = MasterPort('Master port')
  55     req_size = Param.Unsigned(16, "The number of requests to buffer")
  56     resp_size = Param.Unsigned(16, "The number of responses to buffer")
  57     delay = Param.Latency('0ns', "The latency of this serial_link")
  58     ranges = VectorParam.AddrRange([AllMemory],
  59                             "Address ranges to pass through the serial_link")
  60     # Bandwidth of the serial link is determined by the clock domain which the
  61     #  link belongs to and the number of lanes:
  62     num_lanes = Param.Unsigned(1, "Number of parallel lanes inside the serial"
  63         "link. (aka. lane width)")
  64     link_speed = Param.UInt64(1, "Gb/s Speed of each parallel lane inside the"
  65         "serial link. (aka. lane speed)")