src/mem/SerialLink.py

   1 # Copyright (c) 2012-2013 ARM Limited
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  13 # Copyright (c) 2006-2007 The Regents of The University of Michigan
  14 # Copyright (c) 2015 The University of Bologna
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  39
  40 from m5.params import *
  41 from m5.objects.ClockedObject import ClockedObject
  42
  43 # SerialLink is a simple variation of the Bridge class, with the ability to
  44 # account for the latency of packet serialization.
  45
  46 class SerialLink(ClockedObject):
  47     type = 'SerialLink'
  48     cxx_header = "mem/serial_link.hh"
  49     mem_side_port = RequestPort("This port sends requests and "
  50                                             "receives responses")
  51     master   = DeprecatedParam(mem_side_port,
  52                                 '`master` is now called `mem_side_port`')
  53     cpu_side_port = ResponsePort("This port receives requests and "
  54                                                     "sends responses")
  55     slave    = DeprecatedParam(cpu_side_port,
  56                                 '`slave` is now called `cpu_side_port`')
  57     req_size = Param.Unsigned(16, "The number of requests to buffer")
  58     resp_size = Param.Unsigned(16, "The number of responses to buffer")
  59     delay = Param.Latency('0ns', "The latency of this serial_link")
  60     ranges = VectorParam.AddrRange([AllMemory],
  61                             "Address ranges to pass through the serial_link")
  62     # Bandwidth of the serial link is determined by the clock domain which the
  63     #  link belongs to and the number of lanes:
  64     num_lanes = Param.Unsigned(1, "Number of parallel lanes inside the serial"
  65         "link. (aka. lane width)")
  66     link_speed = Param.UInt64(1, "Gb/s Speed of each parallel lane inside the"
  67         "serial link. (aka. lane speed)")