src/mem/SimpleDRAM.py

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  35 #
  36 # Authors: Andreas Hansson
  37 #          Ani Udipi
  38
  39 from m5.params import *
  40 from AbstractMemory import *
  41
  42 # Enum for memory scheduling algorithms, currently First-Come
  43 # First-Served and a First-Row Hit then First-Come First-Served
  44 class MemSched(Enum): vals = ['fcfs', 'frfcfs']
  45
  46 # Enum for the address mapping, currently corresponding to either
  47 # optimising for sequential accesses hitting in the open row, or
  48 # striping across banks.
  49 class AddrMap(Enum): vals = ['openmap', 'closemap']
  50
  51 # Enum for the page policy, either open or close.
  52 class PageManage(Enum): vals = ['open', 'close']
  53
  54 # SimpleDRAM is a single-channel single-ported DRAM controller model
  55 # that aims to model the most important system-level performance
  56 # effects of a DRAM without getting into too much detail of the DRAM
  57 # itself.
  58 class SimpleDRAM(AbstractMemory):
  59     type = 'SimpleDRAM'
  60     cxx_header = "mem/simple_dram.hh"
  61
  62     # single-ported on the system interface side, instantiate with a
  63     # bus in front of the controller for multiple ports
  64     port = SlavePort("Slave port")
  65
  66     # the physical organisation of the DRAM
  67     lines_per_rowbuffer = Param.Unsigned(64, "Row buffer size in cache lines")
  68     ranks_per_channel = Param.Unsigned(2, "Number of ranks per channel")
  69     banks_per_rank = Param.Unsigned(8, "Number of banks per rank")
  70
  71     # the basic configuration of the controller architecture
  72     write_buffer_size = Param.Unsigned(32, "Number of read queue entries")
  73     read_buffer_size = Param.Unsigned(32, "Number of write queue entries")
  74
  75     # threshold in percent for when to trigger writes and start
  76     # emptying the write buffer as it starts to get full
  77     write_thresh_perc = Param.Percent(70, "Threshold to trigger writes")
  78
  79     # scheduler, address map and page policy
  80     mem_sched_policy = Param.MemSched('fcfs', "Memory scheduling policy")
  81     addr_mapping = Param.AddrMap('openmap', "Address mapping policy")
  82     page_policy = Param.PageManage('open', "Page closure management policy")
  83
  84     # timing behaviour and constraints - all in nanoseconds
  85
  86     # the amount of time in nanoseconds from issuing an activate command
  87     # to the data being available in the row buffer for a read/write
  88     tRCD = Param.Latency("14ns", "RAS to CAS delay")
  89
  90     # the time from issuing a read/write command to seeing the actual data
  91     tCL = Param.Latency("14ns", "CAS latency")
  92
  93     # minimum time between a precharge and subsequent activate
  94     tRP = Param.Latency("14ns", "Row precharge time")
  95
  96     # time to complete a burst transfer, typically the burst length
  97     # divided by two due to the DDR bus, but by making it a parameter
  98     # it is easier to also evaluate SDR memories like WideIO.
  99     # This parameter has to account for bus width and burst length.
 100     # Adjustment also necessary if cache line size is greater than
 101     # data size read/written by one full burst.
 102     tBURST = Param.Latency("4ns",
 103                            "Burst duration (for DDR burst length / 2 cycles)")
 104
 105     # time taken to complete one refresh cycle (N rows in all banks)
 106     tRFC = Param.Latency("300ns", "Refresh cycle time")
 107
 108     # refresh command interval, how often a "ref" command needs
 109     # to be sent. It is 7.8 us for a 64ms refresh requirement
 110     tREFI = Param.Latency("7.8us", "Refresh command interval")
 111
 112     # write-to-read turn around penalty, assumed same as read-to-write
 113     tWTR = Param.Latency("1ns", "Write to read switching time")
 114
 115     # time window in which a maximum number of activates are allowed
 116     # to take place, set to 0 to disable
 117     tXAW = Param.Latency("0ns", "X activation window")
 118     activation_limit = Param.Unsigned(4, "Max number of activates in window")
 119
 120     # Currently rolled into other params
 121     ######################################################################
 122
 123     # the minimum amount of time between a row being activated, and
 124     # precharged (de-activated)
 125     # tRAS - assumed to be 3 * tRP
 126
 127     # tRC  - assumed to be 4 * tRP
 128
 129     # burst length for an access derived from peerBlockSize