src/mem/XBar.py

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  38
  39 from m5.objects.System import System
  40 from m5.params import *
  41 from m5.proxy import *
  42 from m5.SimObject import SimObject
  43
  44 from m5.objects.ClockedObject import ClockedObject
  45
  46 class BaseXBar(ClockedObject):
  47     type = 'BaseXBar'
  48     abstract = True
  49     cxx_header = "mem/xbar.hh"
  50
  51     slave = VectorSlavePort("Vector port for connecting masters")
  52     master = VectorMasterPort("Vector port for connecting slaves")
  53
  54     # Latencies governing the time taken for the variuos paths a
  55     # packet has through the crossbar. Note that the crossbar itself
  56     # does not add the latency due to assumptions in the coherency
  57     # mechanism. Instead the latency is annotated on the packet and
  58     # left to the neighbouring modules.
  59     #
  60     # A request incurs the frontend latency, possibly snoop filter
  61     # lookup latency, and forward latency. A response incurs the
  62     # response latency. Frontend latency encompasses arbitration and
  63     # deciding what to do when a request arrives. the forward latency
  64     # is the latency involved once a decision is made to forward the
  65     # request. The response latency, is similar to the forward
  66     # latency, but for responses rather than requests.
  67     frontend_latency = Param.Cycles("Frontend latency")
  68     forward_latency = Param.Cycles("Forward latency")
  69     response_latency = Param.Cycles("Response latency")
  70
  71     # The XBar uses one Layer per master. Each Layer forwards a packet
  72     # to its destination and is occupied for header_latency + size /
  73     # width cycles
  74     header_latency = Param.Cycles(1, "Header latency")
  75
  76     # Width governing the throughput of the crossbar
  77     width = Param.Unsigned("Datapath width per port (bytes)")
  78
  79     # The default port can be left unconnected, or be used to connect
  80     # a default slave port
  81     default = RequestPort("Port for connecting an optional default slave")
  82
  83     # The default port can be used unconditionally, or based on
  84     # address range, in which case it may overlap with other
  85     # ports. The default range is always checked first, thus creating
  86     # a two-level hierarchical lookup. This is useful e.g. for the PCI
  87     # xbar configuration.
  88     use_default_range = Param.Bool(False, "Perform address mapping for " \
  89                                        "the default port")
  90
  91 class NoncoherentXBar(BaseXBar):
  92     type = 'NoncoherentXBar'
  93     cxx_header = "mem/noncoherent_xbar.hh"
  94
  95 class CoherentXBar(BaseXBar):
  96     type = 'CoherentXBar'
  97     cxx_header = "mem/coherent_xbar.hh"
  98
  99     # The coherent crossbar additionally has snoop responses that are
 100     # forwarded after a specific latency.
 101     snoop_response_latency = Param.Cycles("Snoop response latency")
 102
 103     # An optional snoop filter
 104     snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter")
 105
 106     # Maximum number of outstanding snoop requests for sanity checks
 107     max_outstanding_snoops = Param.Int(512, "Max. outstanding snoops allowed")
 108
 109     # Maximum routing table size for sanity checks
 110     max_routing_table_size = Param.Int(512, "Max. routing table size")
 111
 112     # Determine how this crossbar handles packets where caches have
 113     # already committed to responding, by establishing if the crossbar
 114     # is the point of coherency or not.
 115     point_of_coherency = Param.Bool(False, "Consider this crossbar the " \
 116                                     "point of coherency")
 117
 118     # Specify whether this crossbar is the point of unification.
 119     point_of_unification = Param.Bool(False, "Consider this crossbar the " \
 120                                       "point of unification")
 121
 122     system = Param.System(Parent.any, "System that the crossbar belongs to.")
 123
 124 class SnoopFilter(SimObject):
 125     type = 'SnoopFilter'
 126     cxx_header = "mem/snoop_filter.hh"
 127
 128     # Lookup latency of the snoop filter, added to requests that pass
 129     # through a coherent crossbar.
 130     lookup_latency = Param.Cycles(1, "Lookup latency")
 131
 132     system = Param.System(Parent.any, "System that the crossbar belongs to.")
 133
 134     # Sanity check on max capacity to track, adjust if needed.
 135     max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop filter")
 136
 137 # We use a coherent crossbar to connect multiple masters to the L2
 138 # caches. Normally this crossbar would be part of the cache itself.
 139 class L2XBar(CoherentXBar):
 140     # 256-bit crossbar by default
 141     width = 32
 142
 143     # Assume that most of this is covered by the cache latencies, with
 144     # no more than a single pipeline stage for any packet.
 145     frontend_latency = 1
 146     forward_latency = 0
 147     response_latency = 1
 148     snoop_response_latency = 1
 149
 150     # Use a snoop-filter by default, and set the latency to zero as
 151     # the lookup is assumed to overlap with the frontend latency of
 152     # the crossbar
 153     snoop_filter = SnoopFilter(lookup_latency = 0)
 154
 155     # This specialisation of the coherent crossbar is to be considered
 156     # the point of unification, it connects the dcache and the icache
 157     # to the first level of unified cache.
 158     point_of_unification = True
 159
 160 # One of the key coherent crossbar instances is the system
 161 # interconnect, tying together the CPU clusters, GPUs, and any I/O
 162 # coherent masters, and DRAM controllers.
 163 class SystemXBar(CoherentXBar):
 164     # 128-bit crossbar by default
 165     width = 16
 166
 167     # A handful pipeline stages for each portion of the latency
 168     # contributions.
 169     frontend_latency = 3
 170     forward_latency = 4
 171     response_latency = 2
 172     snoop_response_latency = 4
 173
 174     # Use a snoop-filter by default
 175     snoop_filter = SnoopFilter(lookup_latency = 1)
 176
 177     # This specialisation of the coherent crossbar is to be considered
 178     # the point of coherency, as there are no (coherent) downstream
 179     # caches.
 180     point_of_coherency = True
 181
 182     # This specialisation of the coherent crossbar is to be considered
 183     # the point of unification, it connects the dcache and the icache
 184     # to the first level of unified cache. This is needed for systems
 185     # without caches where the SystemXBar is also the point of
 186     # unification.
 187     point_of_unification = True
 188
 189 # In addition to the system interconnect, we typically also have one
 190 # or more on-chip I/O crossbars. Note that at some point we might want
 191 # to also define an off-chip I/O crossbar such as PCIe.
 192 class IOXBar(NoncoherentXBar):
 193     # 128-bit crossbar by default
 194     width = 16
 195
 196     # Assume a simpler datapath than a coherent crossbar, incuring
 197     # less pipeline stages for decision making and forwarding of
 198     # requests.
 199     frontend_latency = 2
 200     forward_latency = 1
 201     response_latency = 2