src/mem/XBar.py

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  13 # Copyright (c) 2005-2008 The Regents of The University of Michigan
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  38
  39 from m5.objects.System import System
  40 from m5.params import *
  41 from m5.proxy import *
  42 from m5.SimObject import SimObject
  43
  44 from m5.objects.ClockedObject import ClockedObject
  45
  46 class BaseXBar(ClockedObject):
  47     type = 'BaseXBar'
  48     abstract = True
  49     cxx_header = "mem/xbar.hh"
  50
  51     cpu_side_ports = VectorResponsePort("Vector port for connecting "
  52                                                 "mem side ports")
  53     slave    = DeprecatedParam(cpu_side_ports,
  54                                 '`slave` is now called `cpu_side_ports`')
  55     mem_side_ports = VectorRequestPort("Vector port for connecting "
  56                                                 "cpu side ports")
  57     master   = DeprecatedParam(mem_side_ports,
  58                                 '`master` is now called `mem_side_ports`')
  59
  60     # Latencies governing the time taken for the variuos paths a
  61     # packet has through the crossbar. Note that the crossbar itself
  62     # does not add the latency due to assumptions in the coherency
  63     # mechanism. Instead the latency is annotated on the packet and
  64     # left to the neighbouring modules.
  65     #
  66     # A request incurs the frontend latency, possibly snoop filter
  67     # lookup latency, and forward latency. A response incurs the
  68     # response latency. Frontend latency encompasses arbitration and
  69     # deciding what to do when a request arrives. the forward latency
  70     # is the latency involved once a decision is made to forward the
  71     # request. The response latency, is similar to the forward
  72     # latency, but for responses rather than requests.
  73     frontend_latency = Param.Cycles("Frontend latency")
  74     forward_latency = Param.Cycles("Forward latency")
  75     response_latency = Param.Cycles("Response latency")
  76
  77     # The XBar uses one Layer per requestor. Each Layer forwards a packet
  78     # to its destination and is occupied for header_latency + size /
  79     # width cycles
  80     header_latency = Param.Cycles(1, "Header latency")
  81
  82     # Width governing the throughput of the crossbar
  83     width = Param.Unsigned("Datapath width per port (bytes)")
  84
  85     # The default port can be left unconnected, or be used to connect
  86     # a default response port
  87     default = RequestPort("Port for connecting an optional default responder")
  88
  89     # The default port can be used unconditionally, or based on
  90     # address range, in which case it may overlap with other
  91     # ports. The default range is always checked first, thus creating
  92     # a two-level hierarchical lookup. This is useful e.g. for the PCI
  93     # xbar configuration.
  94     use_default_range = Param.Bool(False, "Perform address mapping for " \
  95                                        "the default port")
  96
  97 class NoncoherentXBar(BaseXBar):
  98     type = 'NoncoherentXBar'
  99     cxx_header = "mem/noncoherent_xbar.hh"
 100
 101 class CoherentXBar(BaseXBar):
 102     type = 'CoherentXBar'
 103     cxx_header = "mem/coherent_xbar.hh"
 104
 105     # The coherent crossbar additionally has snoop responses that are
 106     # forwarded after a specific latency.
 107     snoop_response_latency = Param.Cycles("Snoop response latency")
 108
 109     # An optional snoop filter
 110     snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter")
 111
 112     # Maximum number of outstanding snoop requests for sanity checks
 113     max_outstanding_snoops = Param.Int(512, "Max. outstanding snoops allowed")
 114
 115     # Maximum routing table size for sanity checks
 116     max_routing_table_size = Param.Int(512, "Max. routing table size")
 117
 118     # Determine how this crossbar handles packets where caches have
 119     # already committed to responding, by establishing if the crossbar
 120     # is the point of coherency or not.
 121     point_of_coherency = Param.Bool(False, "Consider this crossbar the " \
 122                                     "point of coherency")
 123
 124     # Specify whether this crossbar is the point of unification.
 125     point_of_unification = Param.Bool(False, "Consider this crossbar the " \
 126                                       "point of unification")
 127
 128     system = Param.System(Parent.any, "System that the crossbar belongs to.")
 129
 130 class SnoopFilter(SimObject):
 131     type = 'SnoopFilter'
 132     cxx_header = "mem/snoop_filter.hh"
 133
 134     # Lookup latency of the snoop filter, added to requests that pass
 135     # through a coherent crossbar.
 136     lookup_latency = Param.Cycles(1, "Lookup latency")
 137
 138     system = Param.System(Parent.any, "System that the crossbar belongs to.")
 139
 140     # Sanity check on max capacity to track, adjust if needed.
 141     max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop filter")
 142
 143 # We use a coherent crossbar to connect multiple requestors to the L2
 144 # caches. Normally this crossbar would be part of the cache itself.
 145 class L2XBar(CoherentXBar):
 146     # 256-bit crossbar by default
 147     width = 32
 148
 149     # Assume that most of this is covered by the cache latencies, with
 150     # no more than a single pipeline stage for any packet.
 151     frontend_latency = 1
 152     forward_latency = 0
 153     response_latency = 1
 154     snoop_response_latency = 1
 155
 156     # Use a snoop-filter by default, and set the latency to zero as
 157     # the lookup is assumed to overlap with the frontend latency of
 158     # the crossbar
 159     snoop_filter = SnoopFilter(lookup_latency = 0)
 160
 161     # This specialisation of the coherent crossbar is to be considered
 162     # the point of unification, it connects the dcache and the icache
 163     # to the first level of unified cache.
 164     point_of_unification = True
 165
 166 # One of the key coherent crossbar instances is the system
 167 # interconnect, tying together the CPU clusters, GPUs, and any I/O
 168 # coherent requestors, and DRAM controllers.
 169 class SystemXBar(CoherentXBar):
 170     # 128-bit crossbar by default
 171     width = 16
 172
 173     # A handful pipeline stages for each portion of the latency
 174     # contributions.
 175     frontend_latency = 3
 176     forward_latency = 4
 177     response_latency = 2
 178     snoop_response_latency = 4
 179
 180     # Use a snoop-filter by default
 181     snoop_filter = SnoopFilter(lookup_latency = 1)
 182
 183     # This specialisation of the coherent crossbar is to be considered
 184     # the point of coherency, as there are no (coherent) downstream
 185     # caches.
 186     point_of_coherency = True
 187
 188     # This specialisation of the coherent crossbar is to be considered
 189     # the point of unification, it connects the dcache and the icache
 190     # to the first level of unified cache. This is needed for systems
 191     # without caches where the SystemXBar is also the point of
 192     # unification.
 193     point_of_unification = True
 194
 195 # In addition to the system interconnect, we typically also have one
 196 # or more on-chip I/O crossbars. Note that at some point we might want
 197 # to also define an off-chip I/O crossbar such as PCIe.
 198 class IOXBar(NoncoherentXBar):
 199     # 128-bit crossbar by default
 200     width = 16
 201
 202     # Assume a simpler datapath than a coherent crossbar, incuring
 203     # less pipeline stages for decision making and forwarding of
 204     # requests.
 205     frontend_latency = 2
 206     forward_latency = 1
 207     response_latency = 2