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39 # Authors: Nathan Binkert
42 from m5
.objects
.System
import System
43 from m5
.params
import *
44 from m5
.proxy
import *
45 from m5
.SimObject
import SimObject
47 from m5
.objects
.MemObject
import MemObject
49 class BaseXBar(MemObject
):
52 cxx_header
= "mem/xbar.hh"
54 slave
= VectorSlavePort("Vector port for connecting masters")
55 master
= VectorMasterPort("Vector port for connecting slaves")
57 # Latencies governing the time taken for the variuos paths a
58 # packet has through the crossbar. Note that the crossbar itself
59 # does not add the latency due to assumptions in the coherency
60 # mechanism. Instead the latency is annotated on the packet and
61 # left to the neighbouring modules.
63 # A request incurs the frontend latency, possibly snoop filter
64 # lookup latency, and forward latency. A response incurs the
65 # response latency. Frontend latency encompasses arbitration and
66 # deciding what to do when a request arrives. the forward latency
67 # is the latency involved once a decision is made to forward the
68 # request. The response latency, is similar to the forward
69 # latency, but for responses rather than requests.
70 frontend_latency
= Param
.Cycles("Frontend latency")
71 forward_latency
= Param
.Cycles("Forward latency")
72 response_latency
= Param
.Cycles("Response latency")
74 # Width governing the throughput of the crossbar
75 width
= Param
.Unsigned("Datapath width per port (bytes)")
77 # The default port can be left unconnected, or be used to connect
78 # a default slave port
79 default
= MasterPort("Port for connecting an optional default slave")
81 # The default port can be used unconditionally, or based on
82 # address range, in which case it may overlap with other
83 # ports. The default range is always checked first, thus creating
84 # a two-level hierarchical lookup. This is useful e.g. for the PCI
86 use_default_range
= Param
.Bool(False, "Perform address mapping for " \
89 class NoncoherentXBar(BaseXBar
):
90 type = 'NoncoherentXBar'
91 cxx_header
= "mem/noncoherent_xbar.hh"
93 class CoherentXBar(BaseXBar
):
95 cxx_header
= "mem/coherent_xbar.hh"
97 # The coherent crossbar additionally has snoop responses that are
98 # forwarded after a specific latency.
99 snoop_response_latency
= Param
.Cycles("Snoop response latency")
101 # An optional snoop filter
102 snoop_filter
= Param
.SnoopFilter(NULL
, "Selected snoop filter")
104 # Determine how this crossbar handles packets where caches have
105 # already committed to responding, by establishing if the crossbar
106 # is the point of coherency or not.
107 point_of_coherency
= Param
.Bool(False, "Consider this crossbar the " \
108 "point of coherency")
110 # Specify whether this crossbar is the point of unification.
111 point_of_unification
= Param
.Bool(False, "Consider this crossbar the " \
112 "point of unification")
114 system
= Param
.System(Parent
.any
, "System that the crossbar belongs to.")
116 class SnoopFilter(SimObject
):
118 cxx_header
= "mem/snoop_filter.hh"
120 # Lookup latency of the snoop filter, added to requests that pass
121 # through a coherent crossbar.
122 lookup_latency
= Param
.Cycles(1, "Lookup latency")
124 system
= Param
.System(Parent
.any
, "System that the crossbar belongs to.")
126 # Sanity check on max capacity to track, adjust if needed.
127 max_capacity
= Param
.MemorySize('8MB', "Maximum capacity of snoop filter")
129 # We use a coherent crossbar to connect multiple masters to the L2
130 # caches. Normally this crossbar would be part of the cache itself.
131 class L2XBar(CoherentXBar
):
132 # 256-bit crossbar by default
135 # Assume that most of this is covered by the cache latencies, with
136 # no more than a single pipeline stage for any packet.
140 snoop_response_latency
= 1
142 # Use a snoop-filter by default, and set the latency to zero as
143 # the lookup is assumed to overlap with the frontend latency of
145 snoop_filter
= SnoopFilter(lookup_latency
= 0)
147 # This specialisation of the coherent crossbar is to be considered
148 # the point of unification, it connects the dcache and the icache
149 # to the first level of unified cache.
150 point_of_unification
= True
152 # One of the key coherent crossbar instances is the system
153 # interconnect, tying together the CPU clusters, GPUs, and any I/O
154 # coherent masters, and DRAM controllers.
155 class SystemXBar(CoherentXBar
):
156 # 128-bit crossbar by default
159 # A handful pipeline stages for each portion of the latency
164 snoop_response_latency
= 4
166 # Use a snoop-filter by default
167 snoop_filter
= SnoopFilter(lookup_latency
= 1)
169 # This specialisation of the coherent crossbar is to be considered
170 # the point of coherency, as there are no (coherent) downstream
172 point_of_coherency
= True
174 # This specialisation of the coherent crossbar is to be considered
175 # the point of unification, it connects the dcache and the icache
176 # to the first level of unified cache. This is needed for systems
177 # without caches where the SystemXBar is also the point of
179 point_of_unification
= True
181 # In addition to the system interconnect, we typically also have one
182 # or more on-chip I/O crossbars. Note that at some point we might want
183 # to also define an off-chip I/O crossbar such as PCIe.
184 class IOXBar(NoncoherentXBar
):
185 # 128-bit crossbar by default
188 # Assume a simpler datapath than a coherent crossbar, incuring
189 # less pipeline stages for decision making and forwarding of