src/mem/XBar.py

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  13 # Copyright (c) 2005-2008 The Regents of The University of Michigan
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  38
  39 from m5.objects.System import System
  40 from m5.params import *
  41 from m5.proxy import *
  42 from m5.SimObject import SimObject
  43
  44 from m5.objects.ClockedObject import ClockedObject
  45
  46 class BaseXBar(ClockedObject):
  47     type = 'BaseXBar'
  48     abstract = True
  49     cxx_header = "mem/xbar.hh"
  50
  51     slave = VectorSlavePort("Vector port for connecting masters")
  52     master = VectorMasterPort("Vector port for connecting slaves")
  53
  54     # Latencies governing the time taken for the variuos paths a
  55     # packet has through the crossbar. Note that the crossbar itself
  56     # does not add the latency due to assumptions in the coherency
  57     # mechanism. Instead the latency is annotated on the packet and
  58     # left to the neighbouring modules.
  59     #
  60     # A request incurs the frontend latency, possibly snoop filter
  61     # lookup latency, and forward latency. A response incurs the
  62     # response latency. Frontend latency encompasses arbitration and
  63     # deciding what to do when a request arrives. the forward latency
  64     # is the latency involved once a decision is made to forward the
  65     # request. The response latency, is similar to the forward
  66     # latency, but for responses rather than requests.
  67     frontend_latency = Param.Cycles("Frontend latency")
  68     forward_latency = Param.Cycles("Forward latency")
  69     response_latency = Param.Cycles("Response latency")
  70
  71     # Width governing the throughput of the crossbar
  72     width = Param.Unsigned("Datapath width per port (bytes)")
  73
  74     # The default port can be left unconnected, or be used to connect
  75     # a default slave port
  76     default = MasterPort("Port for connecting an optional default slave")
  77
  78     # The default port can be used unconditionally, or based on
  79     # address range, in which case it may overlap with other
  80     # ports. The default range is always checked first, thus creating
  81     # a two-level hierarchical lookup. This is useful e.g. for the PCI
  82     # xbar configuration.
  83     use_default_range = Param.Bool(False, "Perform address mapping for " \
  84                                        "the default port")
  85
  86 class NoncoherentXBar(BaseXBar):
  87     type = 'NoncoherentXBar'
  88     cxx_header = "mem/noncoherent_xbar.hh"
  89
  90 class CoherentXBar(BaseXBar):
  91     type = 'CoherentXBar'
  92     cxx_header = "mem/coherent_xbar.hh"
  93
  94     # The coherent crossbar additionally has snoop responses that are
  95     # forwarded after a specific latency.
  96     snoop_response_latency = Param.Cycles("Snoop response latency")
  97
  98     # An optional snoop filter
  99     snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter")
 100
 101     # Maximum number of outstanding snoop requests for sanity checks
 102     max_outstanding_snoops = Param.Int(512, "Max. outstanding snoops allowed")
 103
 104     # Maximum routing table size for sanity checks
 105     max_routing_table_size = Param.Int(512, "Max. routing table size")
 106
 107     # Determine how this crossbar handles packets where caches have
 108     # already committed to responding, by establishing if the crossbar
 109     # is the point of coherency or not.
 110     point_of_coherency = Param.Bool(False, "Consider this crossbar the " \
 111                                     "point of coherency")
 112
 113     # Specify whether this crossbar is the point of unification.
 114     point_of_unification = Param.Bool(False, "Consider this crossbar the " \
 115                                       "point of unification")
 116
 117     system = Param.System(Parent.any, "System that the crossbar belongs to.")
 118
 119 class SnoopFilter(SimObject):
 120     type = 'SnoopFilter'
 121     cxx_header = "mem/snoop_filter.hh"
 122
 123     # Lookup latency of the snoop filter, added to requests that pass
 124     # through a coherent crossbar.
 125     lookup_latency = Param.Cycles(1, "Lookup latency")
 126
 127     system = Param.System(Parent.any, "System that the crossbar belongs to.")
 128
 129     # Sanity check on max capacity to track, adjust if needed.
 130     max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop filter")
 131
 132 # We use a coherent crossbar to connect multiple masters to the L2
 133 # caches. Normally this crossbar would be part of the cache itself.
 134 class L2XBar(CoherentXBar):
 135     # 256-bit crossbar by default
 136     width = 32
 137
 138     # Assume that most of this is covered by the cache latencies, with
 139     # no more than a single pipeline stage for any packet.
 140     frontend_latency = 1
 141     forward_latency = 0
 142     response_latency = 1
 143     snoop_response_latency = 1
 144
 145     # Use a snoop-filter by default, and set the latency to zero as
 146     # the lookup is assumed to overlap with the frontend latency of
 147     # the crossbar
 148     snoop_filter = SnoopFilter(lookup_latency = 0)
 149
 150     # This specialisation of the coherent crossbar is to be considered
 151     # the point of unification, it connects the dcache and the icache
 152     # to the first level of unified cache.
 153     point_of_unification = True
 154
 155 # One of the key coherent crossbar instances is the system
 156 # interconnect, tying together the CPU clusters, GPUs, and any I/O
 157 # coherent masters, and DRAM controllers.
 158 class SystemXBar(CoherentXBar):
 159     # 128-bit crossbar by default
 160     width = 16
 161
 162     # A handful pipeline stages for each portion of the latency
 163     # contributions.
 164     frontend_latency = 3
 165     forward_latency = 4
 166     response_latency = 2
 167     snoop_response_latency = 4
 168
 169     # Use a snoop-filter by default
 170     snoop_filter = SnoopFilter(lookup_latency = 1)
 171
 172     # This specialisation of the coherent crossbar is to be considered
 173     # the point of coherency, as there are no (coherent) downstream
 174     # caches.
 175     point_of_coherency = True
 176
 177     # This specialisation of the coherent crossbar is to be considered
 178     # the point of unification, it connects the dcache and the icache
 179     # to the first level of unified cache. This is needed for systems
 180     # without caches where the SystemXBar is also the point of
 181     # unification.
 182     point_of_unification = True
 183
 184 # In addition to the system interconnect, we typically also have one
 185 # or more on-chip I/O crossbars. Note that at some point we might want
 186 # to also define an off-chip I/O crossbar such as PCIe.
 187 class IOXBar(NoncoherentXBar):
 188     # 128-bit crossbar by default
 189     width = 16
 190
 191     # Assume a simpler datapath than a coherent crossbar, incuring
 192     # less pipeline stages for decision making and forwarding of
 193     # requests.
 194     frontend_latency = 2
 195     forward_latency = 1
 196     response_latency = 2