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13 # Copyright (c) 2005-2008 The Regents of The University of Michigan
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39 # Authors: Nathan Binkert
42 from MemObject
import MemObject
43 from System
import System
44 from m5
.params
import *
45 from m5
.proxy
import *
46 from m5
.SimObject
import SimObject
48 class BaseXBar(MemObject
):
51 cxx_header
= "mem/xbar.hh"
53 slave
= VectorSlavePort("Vector port for connecting masters")
54 master
= VectorMasterPort("Vector port for connecting slaves")
56 # Latencies governing the time taken for the variuos paths a
57 # packet has through the crossbar. Note that the crossbar itself
58 # does not add the latency due to assumptions in the coherency
59 # mechanism. Instead the latency is annotated on the packet and
60 # left to the neighbouring modules.
62 # A request incurs the frontend latency, possibly snoop filter
63 # lookup latency, and forward latency. A response incurs the
64 # response latency. Frontend latency encompasses arbitration and
65 # deciding what to do when a request arrives. the forward latency
66 # is the latency involved once a decision is made to forward the
67 # request. The response latency, is similar to the forward
68 # latency, but for responses rather than requests.
69 frontend_latency
= Param
.Cycles("Frontend latency")
70 forward_latency
= Param
.Cycles("Forward latency")
71 response_latency
= Param
.Cycles("Response latency")
73 # Width governing the throughput of the crossbar
74 width
= Param
.Unsigned("Datapath width per port (bytes)")
76 # The default port can be left unconnected, or be used to connect
77 # a default slave port
78 default
= MasterPort("Port for connecting an optional default slave")
80 # The default port can be used unconditionally, or based on
81 # address range, in which case it may overlap with other
82 # ports. The default range is always checked first, thus creating
83 # a two-level hierarchical lookup. This is useful e.g. for the PCI
85 use_default_range
= Param
.Bool(False, "Perform address mapping for " \
88 class NoncoherentXBar(BaseXBar
):
89 type = 'NoncoherentXBar'
90 cxx_header
= "mem/noncoherent_xbar.hh"
92 class CoherentXBar(BaseXBar
):
94 cxx_header
= "mem/coherent_xbar.hh"
96 # The coherent crossbar additionally has snoop responses that are
97 # forwarded after a specific latency.
98 snoop_response_latency
= Param
.Cycles("Snoop response latency")
100 # An optional snoop filter
101 snoop_filter
= Param
.SnoopFilter(NULL
, "Selected snoop filter")
103 # Determine how this crossbar handles packets where caches have
104 # already committed to responding, by establishing if the crossbar
105 # is the point of coherency or not.
106 point_of_coherency
= Param
.Bool(False, "Consider this crossbar the " \
107 "point of coherency")
109 system
= Param
.System(Parent
.any
, "System that the crossbar belongs to.")
111 class SnoopFilter(SimObject
):
113 cxx_header
= "mem/snoop_filter.hh"
115 # Lookup latency of the snoop filter, added to requests that pass
116 # through a coherent crossbar.
117 lookup_latency
= Param
.Cycles(1, "Lookup latency")
119 system
= Param
.System(Parent
.any
, "System that the crossbar belongs to.")
121 # Sanity check on max capacity to track, adjust if needed.
122 max_capacity
= Param
.MemorySize('8MB', "Maximum capacity of snoop filter")
124 # We use a coherent crossbar to connect multiple masters to the L2
125 # caches. Normally this crossbar would be part of the cache itself.
126 class L2XBar(CoherentXBar
):
127 # 256-bit crossbar by default
130 # Assume that most of this is covered by the cache latencies, with
131 # no more than a single pipeline stage for any packet.
135 snoop_response_latency
= 1
137 # Use a snoop-filter by default, and set the latency to zero as
138 # the lookup is assumed to overlap with the frontend latency of
140 snoop_filter
= SnoopFilter(lookup_latency
= 0)
142 # One of the key coherent crossbar instances is the system
143 # interconnect, tying together the CPU clusters, GPUs, and any I/O
144 # coherent masters, and DRAM controllers.
145 class SystemXBar(CoherentXBar
):
146 # 128-bit crossbar by default
149 # A handful pipeline stages for each portion of the latency
154 snoop_response_latency
= 4
156 # This specialisation of the coherent crossbar is to be considered
157 # the point of coherency, as there are no (coherent) downstream
159 point_of_coherency
= True
161 # In addition to the system interconnect, we typically also have one
162 # or more on-chip I/O crossbars. Note that at some point we might want
163 # to also define an off-chip I/O crossbar such as PCIe.
164 class IOXBar(NoncoherentXBar
):
165 # 128-bit crossbar by default
168 # Assume a simpler datapath than a coherent crossbar, incuring
169 # less pipeline stages for decision making and forwarding of