2 * Copyright (c) 2010-2012,2017 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Ron Dreslinski
45 #include "mem/abstract_mem.hh"
49 #include "arch/locked_mem.hh"
50 #include "cpu/base.hh"
51 #include "cpu/thread_context.hh"
52 #include "debug/LLSC.hh"
53 #include "debug/MemoryAccess.hh"
54 #include "mem/packet_access.hh"
55 #include "sim/system.hh"
59 AbstractMemory::AbstractMemory(const Params
*p
) :
60 MemObject(p
), range(params()->range
), pmemAddr(NULL
),
61 confTableReported(p
->conf_table_reported
), inAddrMap(p
->in_addr_map
),
62 kvmMap(p
->kvm_map
), _system(NULL
)
67 AbstractMemory::init()
71 if (size() % _system
->getPageBytes() != 0)
72 panic("Memory Size not divisible by page size\n");
76 AbstractMemory::setBackingStore(uint8_t* pmem_addr
)
82 AbstractMemory::regStats()
84 MemObject::regStats();
86 using namespace Stats
;
91 .init(system()->maxMasters())
92 .name(name() + ".bytes_read")
93 .desc("Number of bytes read from this memory")
94 .flags(total
| nozero
| nonan
)
96 for (int i
= 0; i
< system()->maxMasters(); i
++) {
97 bytesRead
.subname(i
, system()->getMasterName(i
));
100 .init(system()->maxMasters())
101 .name(name() + ".bytes_inst_read")
102 .desc("Number of instructions bytes read from this memory")
103 .flags(total
| nozero
| nonan
)
105 for (int i
= 0; i
< system()->maxMasters(); i
++) {
106 bytesInstRead
.subname(i
, system()->getMasterName(i
));
109 .init(system()->maxMasters())
110 .name(name() + ".bytes_written")
111 .desc("Number of bytes written to this memory")
112 .flags(total
| nozero
| nonan
)
114 for (int i
= 0; i
< system()->maxMasters(); i
++) {
115 bytesWritten
.subname(i
, system()->getMasterName(i
));
118 .init(system()->maxMasters())
119 .name(name() + ".num_reads")
120 .desc("Number of read requests responded to by this memory")
121 .flags(total
| nozero
| nonan
)
123 for (int i
= 0; i
< system()->maxMasters(); i
++) {
124 numReads
.subname(i
, system()->getMasterName(i
));
127 .init(system()->maxMasters())
128 .name(name() + ".num_writes")
129 .desc("Number of write requests responded to by this memory")
130 .flags(total
| nozero
| nonan
)
132 for (int i
= 0; i
< system()->maxMasters(); i
++) {
133 numWrites
.subname(i
, system()->getMasterName(i
));
136 .init(system()->maxMasters())
137 .name(name() + ".num_other")
138 .desc("Number of other requests responded to by this memory")
139 .flags(total
| nozero
| nonan
)
141 for (int i
= 0; i
< system()->maxMasters(); i
++) {
142 numOther
.subname(i
, system()->getMasterName(i
));
145 .name(name() + ".bw_read")
146 .desc("Total read bandwidth from this memory (bytes/s)")
149 .flags(total
| nozero
| nonan
)
151 for (int i
= 0; i
< system()->maxMasters(); i
++) {
152 bwRead
.subname(i
, system()->getMasterName(i
));
156 .name(name() + ".bw_inst_read")
157 .desc("Instruction read bandwidth from this memory (bytes/s)")
159 .prereq(bytesInstRead
)
160 .flags(total
| nozero
| nonan
)
162 for (int i
= 0; i
< system()->maxMasters(); i
++) {
163 bwInstRead
.subname(i
, system()->getMasterName(i
));
166 .name(name() + ".bw_write")
167 .desc("Write bandwidth from this memory (bytes/s)")
169 .prereq(bytesWritten
)
170 .flags(total
| nozero
| nonan
)
172 for (int i
= 0; i
< system()->maxMasters(); i
++) {
173 bwWrite
.subname(i
, system()->getMasterName(i
));
176 .name(name() + ".bw_total")
177 .desc("Total bandwidth to/from this memory (bytes/s)")
180 .flags(total
| nozero
| nonan
)
182 for (int i
= 0; i
< system()->maxMasters(); i
++) {
183 bwTotal
.subname(i
, system()->getMasterName(i
));
185 bwRead
= bytesRead
/ simSeconds
;
186 bwInstRead
= bytesInstRead
/ simSeconds
;
187 bwWrite
= bytesWritten
/ simSeconds
;
188 bwTotal
= (bytesRead
+ bytesWritten
) / simSeconds
;
192 AbstractMemory::getAddrRange() const
197 // Add load-locked to tracking list. Should only be called if the
198 // operation is a load and the LLSC flag is set.
200 AbstractMemory::trackLoadLocked(PacketPtr pkt
)
202 const RequestPtr
&req
= pkt
->req
;
203 Addr paddr
= LockedAddr::mask(req
->getPaddr());
205 // first we check if we already have a locked addr for this
206 // xc. Since each xc only gets one, we just update the
207 // existing record with the new address.
208 list
<LockedAddr
>::iterator i
;
210 for (i
= lockedAddrList
.begin(); i
!= lockedAddrList
.end(); ++i
) {
211 if (i
->matchesContext(req
)) {
212 DPRINTF(LLSC
, "Modifying lock record: context %d addr %#x\n",
213 req
->contextId(), paddr
);
219 // no record for this xc: need to allocate a new one
220 DPRINTF(LLSC
, "Adding lock record: context %d addr %#x\n",
221 req
->contextId(), paddr
);
222 lockedAddrList
.push_front(LockedAddr(req
));
226 // Called on *writes* only... both regular stores and
227 // store-conditional operations. Check for conventional stores which
228 // conflict with locked addresses, and for success/failure of store
231 AbstractMemory::checkLockedAddrList(PacketPtr pkt
)
233 const RequestPtr
&req
= pkt
->req
;
234 Addr paddr
= LockedAddr::mask(req
->getPaddr());
235 bool isLLSC
= pkt
->isLLSC();
237 // Initialize return value. Non-conditional stores always
238 // succeed. Assume conditional stores will fail until proven
240 bool allowStore
= !isLLSC
;
242 // Iterate over list. Note that there could be multiple matching records,
243 // as more than one context could have done a load locked to this location.
244 // Only remove records when we succeed in finding a record for (xc, addr);
245 // then, remove all records with this address. Failed store-conditionals do
246 // not blow unrelated reservations.
247 list
<LockedAddr
>::iterator i
= lockedAddrList
.begin();
250 while (i
!= lockedAddrList
.end()) {
251 if (i
->addr
== paddr
&& i
->matchesContext(req
)) {
252 // it's a store conditional, and as far as the memory system can
253 // tell, the requesting context's lock is still valid.
254 DPRINTF(LLSC
, "StCond success: context %d addr %#x\n",
255 req
->contextId(), paddr
);
259 // If we didn't find a match, keep searching! Someone else may well
260 // have a reservation on this line here but we may find ours in just
264 req
->setExtraData(allowStore
? 1 : 0);
266 // LLSCs that succeeded AND non-LLSC stores both fall into here:
268 // We write address paddr. However, there may be several entries with a
269 // reservation on this address (for other contextIds) and they must all
271 i
= lockedAddrList
.begin();
272 while (i
!= lockedAddrList
.end()) {
273 if (i
->addr
== paddr
) {
274 DPRINTF(LLSC
, "Erasing lock record: context %d addr %#x\n",
275 i
->contextId
, paddr
);
276 ContextID owner_cid
= i
->contextId
;
277 ContextID requester_cid
= pkt
->req
->contextId();
278 if (owner_cid
!= requester_cid
) {
279 ThreadContext
* ctx
= system()->getThreadContext(owner_cid
);
280 TheISA::globalClearExclusive(ctx
);
282 i
= lockedAddrList
.erase(i
);
293 tracePacket(System
*sys
, const char *label
, PacketPtr pkt
)
295 int size
= pkt
->getSize();
296 #if THE_ISA != NULL_ISA
297 if (size
== 1 || size
== 2 || size
== 4 || size
== 8) {
298 DPRINTF(MemoryAccess
,"%s from %s of size %i on address %#x data "
299 "%#x %c\n", label
, sys
->getMasterName(pkt
->req
->masterId()),
300 size
, pkt
->getAddr(), pkt
->getUintX(TheISA::GuestByteOrder
),
301 pkt
->req
->isUncacheable() ? 'U' : 'C');
305 DPRINTF(MemoryAccess
, "%s from %s of size %i on address %#x %c\n",
306 label
, sys
->getMasterName(pkt
->req
->masterId()),
307 size
, pkt
->getAddr(), pkt
->req
->isUncacheable() ? 'U' : 'C');
308 DDUMP(MemoryAccess
, pkt
->getConstPtr
<uint8_t>(), pkt
->getSize());
312 # define TRACE_PACKET(A) tracePacket(system(), A, pkt)
314 # define TRACE_PACKET(A)
318 AbstractMemory::access(PacketPtr pkt
)
320 if (pkt
->cacheResponding()) {
321 DPRINTF(MemoryAccess
, "Cache responding to %#llx: not responding\n",
326 if (pkt
->cmd
== MemCmd::CleanEvict
|| pkt
->cmd
== MemCmd::WritebackClean
) {
327 DPRINTF(MemoryAccess
, "CleanEvict on 0x%x: not responding\n",
332 assert(AddrRange(pkt
->getAddr(),
333 pkt
->getAddr() + (pkt
->getSize() - 1)).isSubset(range
));
335 uint8_t *hostAddr
= pmemAddr
+ pkt
->getAddr() - range
.start();
337 if (pkt
->cmd
== MemCmd::SwapReq
) {
338 if (pkt
->isAtomicOp()) {
340 memcpy(pkt
->getPtr
<uint8_t>(), hostAddr
, pkt
->getSize());
341 (*(pkt
->getAtomicOp()))(hostAddr
);
344 std::vector
<uint8_t> overwrite_val(pkt
->getSize());
345 uint64_t condition_val64
;
346 uint32_t condition_val32
;
349 panic("Swap only works if there is real memory (i.e. null=False)");
351 bool overwrite_mem
= true;
352 // keep a copy of our possible write value, and copy what is at the
353 // memory address into the packet
354 std::memcpy(&overwrite_val
[0], pkt
->getConstPtr
<uint8_t>(),
356 std::memcpy(pkt
->getPtr
<uint8_t>(), hostAddr
, pkt
->getSize());
358 if (pkt
->req
->isCondSwap()) {
359 if (pkt
->getSize() == sizeof(uint64_t)) {
360 condition_val64
= pkt
->req
->getExtraData();
361 overwrite_mem
= !std::memcmp(&condition_val64
, hostAddr
,
363 } else if (pkt
->getSize() == sizeof(uint32_t)) {
364 condition_val32
= (uint32_t)pkt
->req
->getExtraData();
365 overwrite_mem
= !std::memcmp(&condition_val32
, hostAddr
,
368 panic("Invalid size for conditional read/write\n");
372 std::memcpy(hostAddr
, &overwrite_val
[0], pkt
->getSize());
374 assert(!pkt
->req
->isInstFetch());
375 TRACE_PACKET("Read/Write");
376 numOther
[pkt
->req
->masterId()]++;
378 } else if (pkt
->isRead()) {
379 assert(!pkt
->isWrite());
381 assert(!pkt
->fromCache());
382 // if the packet is not coming from a cache then we have
383 // to do the LL/SC tracking here
384 trackLoadLocked(pkt
);
387 memcpy(pkt
->getPtr
<uint8_t>(), hostAddr
, pkt
->getSize());
388 TRACE_PACKET(pkt
->req
->isInstFetch() ? "IFetch" : "Read");
389 numReads
[pkt
->req
->masterId()]++;
390 bytesRead
[pkt
->req
->masterId()] += pkt
->getSize();
391 if (pkt
->req
->isInstFetch())
392 bytesInstRead
[pkt
->req
->masterId()] += pkt
->getSize();
393 } else if (pkt
->isInvalidate() || pkt
->isClean()) {
394 assert(!pkt
->isWrite());
395 // in a fastmem system invalidating and/or cleaning packets
396 // can be seen due to cache maintenance requests
398 // no need to do anything
399 } else if (pkt
->isWrite()) {
402 memcpy(hostAddr
, pkt
->getConstPtr
<uint8_t>(), pkt
->getSize());
403 DPRINTF(MemoryAccess
, "%s wrote %i bytes to address %x\n",
404 __func__
, pkt
->getSize(), pkt
->getAddr());
406 assert(!pkt
->req
->isInstFetch());
407 TRACE_PACKET("Write");
408 numWrites
[pkt
->req
->masterId()]++;
409 bytesWritten
[pkt
->req
->masterId()] += pkt
->getSize();
412 panic("Unexpected packet %s", pkt
->print());
415 if (pkt
->needsResponse()) {
421 AbstractMemory::functionalAccess(PacketPtr pkt
)
423 assert(AddrRange(pkt
->getAddr(),
424 pkt
->getAddr() + pkt
->getSize() - 1).isSubset(range
));
426 uint8_t *hostAddr
= pmemAddr
+ pkt
->getAddr() - range
.start();
430 memcpy(pkt
->getPtr
<uint8_t>(), hostAddr
, pkt
->getSize());
431 TRACE_PACKET("Read");
433 } else if (pkt
->isWrite()) {
435 memcpy(hostAddr
, pkt
->getConstPtr
<uint8_t>(), pkt
->getSize());
436 TRACE_PACKET("Write");
438 } else if (pkt
->isPrint()) {
439 Packet::PrintReqState
*prs
=
440 dynamic_cast<Packet::PrintReqState
*>(pkt
->senderState
);
442 // Need to call printLabels() explicitly since we're not going
443 // through printObj().
445 // Right now we just print the single byte at the specified address.
446 ccprintf(prs
->os
, "%s%#x\n", prs
->curPrefix(), *hostAddr
);
448 panic("AbstractMemory: unimplemented functional command %s",