2 * Copyright (c) 2010-2012,2017-2019 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #include "mem/abstract_mem.hh"
45 #include "arch/locked_mem.hh"
46 #include "base/loader/memory_image.hh"
47 #include "base/loader/object_file.hh"
48 #include "cpu/thread_context.hh"
49 #include "debug/LLSC.hh"
50 #include "debug/MemoryAccess.hh"
51 #include "mem/packet_access.hh"
52 #include "sim/system.hh"
56 AbstractMemory::AbstractMemory(const Params
*p
) :
57 ClockedObject(p
), range(params()->range
), pmemAddr(NULL
),
58 backdoor(params()->range
, nullptr,
59 (MemBackdoor::Flags
)(MemBackdoor::Readable
|
60 MemBackdoor::Writeable
)),
61 confTableReported(p
->conf_table_reported
), inAddrMap(p
->in_addr_map
),
62 kvmMap(p
->kvm_map
), _system(NULL
),
65 panic_if(!range
.valid() || !range
.size(),
66 "Memory range %s must be valid with non-zero size.",
71 AbstractMemory::initState()
73 ClockedObject::initState();
75 const auto &file
= params()->image_file
;
79 auto *object
= Loader::createObjectFile(file
, true);
80 fatal_if(!object
, "%s: Could not load %s.", name(), file
);
82 Loader::debugSymbolTable
.insert(*object
->symtab().globals());
83 Loader::MemoryImage image
= object
->buildImage();
85 AddrRange
image_range(image
.minAddr(), image
.maxAddr());
86 if (!range
.contains(image_range
.start())) {
87 warn("%s: Moving image from %s to memory address range %s.",
88 name(), image_range
.to_string(), range
.to_string());
89 image
= image
.offset(range
.start());
90 image_range
= AddrRange(image
.minAddr(), image
.maxAddr());
92 panic_if(!image_range
.isSubset(range
), "%s: memory image %s doesn't fit.",
95 PortProxy
proxy([this](PacketPtr pkt
) { functionalAccess(pkt
); }, size());
97 panic_if(!image
.write(proxy
), "%s: Unable to write image.");
101 AbstractMemory::setBackingStore(uint8_t* pmem_addr
)
103 // If there was an existing backdoor, let everybody know it's going away.
105 backdoor
.invalidate();
107 // The back door can't handle interleaved memory.
108 backdoor
.ptr(range
.interleaved() ? nullptr : pmem_addr
);
110 pmemAddr
= pmem_addr
;
113 AbstractMemory::MemStats::MemStats(AbstractMemory
&_mem
)
114 : Stats::Group(&_mem
), mem(_mem
),
115 bytesRead(this, "bytes_read",
116 "Number of bytes read from this memory"),
117 bytesInstRead(this, "bytes_inst_read",
118 "Number of instructions bytes read from this memory"),
119 bytesWritten(this, "bytes_written",
120 "Number of bytes written to this memory"),
121 numReads(this, "num_reads",
122 "Number of read requests responded to by this memory"),
123 numWrites(this, "num_writes",
124 "Number of write requests responded to by this memory"),
125 numOther(this, "num_other",
126 "Number of other requests responded to by this memory"),
127 bwRead(this, "bw_read",
128 "Total read bandwidth from this memory (bytes/s)"),
129 bwInstRead(this, "bw_inst_read",
130 "Instruction read bandwidth from this memory (bytes/s)"),
131 bwWrite(this, "bw_write",
132 "Write bandwidth from this memory (bytes/s)"),
133 bwTotal(this, "bw_total",
134 "Total bandwidth to/from this memory (bytes/s)")
139 AbstractMemory::MemStats::regStats()
141 using namespace Stats
;
143 Stats::Group::regStats();
145 System
*sys
= mem
.system();
147 const auto max_requestors
= sys
->maxRequestors();
150 .init(max_requestors
)
151 .flags(total
| nozero
| nonan
)
153 for (int i
= 0; i
< max_requestors
; i
++) {
154 bytesRead
.subname(i
, sys
->getRequestorName(i
));
158 .init(max_requestors
)
159 .flags(total
| nozero
| nonan
)
161 for (int i
= 0; i
< max_requestors
; i
++) {
162 bytesInstRead
.subname(i
, sys
->getRequestorName(i
));
166 .init(max_requestors
)
167 .flags(total
| nozero
| nonan
)
169 for (int i
= 0; i
< max_requestors
; i
++) {
170 bytesWritten
.subname(i
, sys
->getRequestorName(i
));
174 .init(max_requestors
)
175 .flags(total
| nozero
| nonan
)
177 for (int i
= 0; i
< max_requestors
; i
++) {
178 numReads
.subname(i
, sys
->getRequestorName(i
));
182 .init(max_requestors
)
183 .flags(total
| nozero
| nonan
)
185 for (int i
= 0; i
< max_requestors
; i
++) {
186 numWrites
.subname(i
, sys
->getRequestorName(i
));
190 .init(max_requestors
)
191 .flags(total
| nozero
| nonan
)
193 for (int i
= 0; i
< max_requestors
; i
++) {
194 numOther
.subname(i
, sys
->getRequestorName(i
));
200 .flags(total
| nozero
| nonan
)
202 for (int i
= 0; i
< max_requestors
; i
++) {
203 bwRead
.subname(i
, sys
->getRequestorName(i
));
208 .prereq(bytesInstRead
)
209 .flags(total
| nozero
| nonan
)
211 for (int i
= 0; i
< max_requestors
; i
++) {
212 bwInstRead
.subname(i
, sys
->getRequestorName(i
));
217 .prereq(bytesWritten
)
218 .flags(total
| nozero
| nonan
)
220 for (int i
= 0; i
< max_requestors
; i
++) {
221 bwWrite
.subname(i
, sys
->getRequestorName(i
));
227 .flags(total
| nozero
| nonan
)
229 for (int i
= 0; i
< max_requestors
; i
++) {
230 bwTotal
.subname(i
, sys
->getRequestorName(i
));
233 bwRead
= bytesRead
/ simSeconds
;
234 bwInstRead
= bytesInstRead
/ simSeconds
;
235 bwWrite
= bytesWritten
/ simSeconds
;
236 bwTotal
= (bytesRead
+ bytesWritten
) / simSeconds
;
240 AbstractMemory::getAddrRange() const
245 // Add load-locked to tracking list. Should only be called if the
246 // operation is a load and the LLSC flag is set.
248 AbstractMemory::trackLoadLocked(PacketPtr pkt
)
250 const RequestPtr
&req
= pkt
->req
;
251 Addr paddr
= LockedAddr::mask(req
->getPaddr());
253 // first we check if we already have a locked addr for this
254 // xc. Since each xc only gets one, we just update the
255 // existing record with the new address.
256 list
<LockedAddr
>::iterator i
;
258 for (i
= lockedAddrList
.begin(); i
!= lockedAddrList
.end(); ++i
) {
259 if (i
->matchesContext(req
)) {
260 DPRINTF(LLSC
, "Modifying lock record: context %d addr %#x\n",
261 req
->contextId(), paddr
);
267 // no record for this xc: need to allocate a new one
268 DPRINTF(LLSC
, "Adding lock record: context %d addr %#x\n",
269 req
->contextId(), paddr
);
270 lockedAddrList
.push_front(LockedAddr(req
));
274 // Called on *writes* only... both regular stores and
275 // store-conditional operations. Check for conventional stores which
276 // conflict with locked addresses, and for success/failure of store
279 AbstractMemory::checkLockedAddrList(PacketPtr pkt
)
281 const RequestPtr
&req
= pkt
->req
;
282 Addr paddr
= LockedAddr::mask(req
->getPaddr());
283 bool isLLSC
= pkt
->isLLSC();
285 // Initialize return value. Non-conditional stores always
286 // succeed. Assume conditional stores will fail until proven
288 bool allowStore
= !isLLSC
;
290 // Iterate over list. Note that there could be multiple matching records,
291 // as more than one context could have done a load locked to this location.
292 // Only remove records when we succeed in finding a record for (xc, addr);
293 // then, remove all records with this address. Failed store-conditionals do
294 // not blow unrelated reservations.
295 list
<LockedAddr
>::iterator i
= lockedAddrList
.begin();
298 while (i
!= lockedAddrList
.end()) {
299 if (i
->addr
== paddr
&& i
->matchesContext(req
)) {
300 // it's a store conditional, and as far as the memory system can
301 // tell, the requesting context's lock is still valid.
302 DPRINTF(LLSC
, "StCond success: context %d addr %#x\n",
303 req
->contextId(), paddr
);
307 // If we didn't find a match, keep searching! Someone else may well
308 // have a reservation on this line here but we may find ours in just
312 req
->setExtraData(allowStore
? 1 : 0);
314 // LLSCs that succeeded AND non-LLSC stores both fall into here:
316 // We write address paddr. However, there may be several entries with a
317 // reservation on this address (for other contextIds) and they must all
319 i
= lockedAddrList
.begin();
320 while (i
!= lockedAddrList
.end()) {
321 if (i
->addr
== paddr
) {
322 DPRINTF(LLSC
, "Erasing lock record: context %d addr %#x\n",
323 i
->contextId
, paddr
);
324 ContextID owner_cid
= i
->contextId
;
325 assert(owner_cid
!= InvalidContextID
);
326 ContextID requestor_cid
= req
->hasContextId() ?
329 if (owner_cid
!= requestor_cid
) {
330 ThreadContext
* ctx
= system()->threads
[owner_cid
];
331 TheISA::globalClearExclusive(ctx
);
333 i
= lockedAddrList
.erase(i
);
345 tracePacket(System
*sys
, const char *label
, PacketPtr pkt
)
347 int size
= pkt
->getSize();
348 #if THE_ISA != NULL_ISA
349 if (size
== 1 || size
== 2 || size
== 4 || size
== 8) {
350 ByteOrder byte_order
= sys
->getGuestByteOrder();
351 DPRINTF(MemoryAccess
,"%s from %s of size %i on address %#x data "
352 "%#x %c\n", label
, sys
->getRequestorName(pkt
->req
->
353 requestorId()), size
, pkt
->getAddr(),
354 size
, pkt
->getAddr(), pkt
->getUintX(byte_order
),
355 pkt
->req
->isUncacheable() ? 'U' : 'C');
359 DPRINTF(MemoryAccess
, "%s from %s of size %i on address %#x %c\n",
360 label
, sys
->getRequestorName(pkt
->req
->requestorId()),
361 size
, pkt
->getAddr(), pkt
->req
->isUncacheable() ? 'U' : 'C');
362 DDUMP(MemoryAccess
, pkt
->getConstPtr
<uint8_t>(), pkt
->getSize());
365 # define TRACE_PACKET(A) tracePacket(system(), A, pkt)
367 # define TRACE_PACKET(A)
371 AbstractMemory::access(PacketPtr pkt
)
373 if (pkt
->cacheResponding()) {
374 DPRINTF(MemoryAccess
, "Cache responding to %#llx: not responding\n",
379 if (pkt
->cmd
== MemCmd::CleanEvict
|| pkt
->cmd
== MemCmd::WritebackClean
) {
380 DPRINTF(MemoryAccess
, "CleanEvict on 0x%x: not responding\n",
385 assert(pkt
->getAddrRange().isSubset(range
));
387 uint8_t *host_addr
= toHostAddr(pkt
->getAddr());
389 if (pkt
->cmd
== MemCmd::SwapReq
) {
390 if (pkt
->isAtomicOp()) {
392 pkt
->setData(host_addr
);
393 (*(pkt
->getAtomicOp()))(host_addr
);
396 std::vector
<uint8_t> overwrite_val(pkt
->getSize());
397 uint64_t condition_val64
;
398 uint32_t condition_val32
;
400 panic_if(!pmemAddr
, "Swap only works if there is real memory " \
401 "(i.e. null=False)");
403 bool overwrite_mem
= true;
404 // keep a copy of our possible write value, and copy what is at the
405 // memory address into the packet
406 pkt
->writeData(&overwrite_val
[0]);
407 pkt
->setData(host_addr
);
409 if (pkt
->req
->isCondSwap()) {
410 if (pkt
->getSize() == sizeof(uint64_t)) {
411 condition_val64
= pkt
->req
->getExtraData();
412 overwrite_mem
= !std::memcmp(&condition_val64
, host_addr
,
414 } else if (pkt
->getSize() == sizeof(uint32_t)) {
415 condition_val32
= (uint32_t)pkt
->req
->getExtraData();
416 overwrite_mem
= !std::memcmp(&condition_val32
, host_addr
,
419 panic("Invalid size for conditional read/write\n");
423 std::memcpy(host_addr
, &overwrite_val
[0], pkt
->getSize());
425 assert(!pkt
->req
->isInstFetch());
426 TRACE_PACKET("Read/Write");
427 stats
.numOther
[pkt
->req
->requestorId()]++;
429 } else if (pkt
->isRead()) {
430 assert(!pkt
->isWrite());
432 assert(!pkt
->fromCache());
433 // if the packet is not coming from a cache then we have
434 // to do the LL/SC tracking here
435 trackLoadLocked(pkt
);
438 pkt
->setData(host_addr
);
440 TRACE_PACKET(pkt
->req
->isInstFetch() ? "IFetch" : "Read");
441 stats
.numReads
[pkt
->req
->requestorId()]++;
442 stats
.bytesRead
[pkt
->req
->requestorId()] += pkt
->getSize();
443 if (pkt
->req
->isInstFetch())
444 stats
.bytesInstRead
[pkt
->req
->requestorId()] += pkt
->getSize();
445 } else if (pkt
->isInvalidate() || pkt
->isClean()) {
446 assert(!pkt
->isWrite());
447 // in a fastmem system invalidating and/or cleaning packets
448 // can be seen due to cache maintenance requests
450 // no need to do anything
451 } else if (pkt
->isWrite()) {
454 pkt
->writeData(host_addr
);
455 DPRINTF(MemoryAccess
, "%s write due to %s\n",
456 __func__
, pkt
->print());
458 assert(!pkt
->req
->isInstFetch());
459 TRACE_PACKET("Write");
460 stats
.numWrites
[pkt
->req
->requestorId()]++;
461 stats
.bytesWritten
[pkt
->req
->requestorId()] += pkt
->getSize();
464 panic("Unexpected packet %s", pkt
->print());
467 if (pkt
->needsResponse()) {
473 AbstractMemory::functionalAccess(PacketPtr pkt
)
475 assert(pkt
->getAddrRange().isSubset(range
));
477 uint8_t *host_addr
= toHostAddr(pkt
->getAddr());
481 pkt
->setData(host_addr
);
483 TRACE_PACKET("Read");
485 } else if (pkt
->isWrite()) {
487 pkt
->writeData(host_addr
);
489 TRACE_PACKET("Write");
491 } else if (pkt
->isPrint()) {
492 Packet::PrintReqState
*prs
=
493 dynamic_cast<Packet::PrintReqState
*>(pkt
->senderState
);
495 // Need to call printLabels() explicitly since we're not going
496 // through printObj().
498 // Right now we just print the single byte at the specified address.
499 ccprintf(prs
->os
, "%s%#x\n", prs
->curPrefix(), *host_addr
);
501 panic("AbstractMemory: unimplemented functional command %s",