2 * Copyright (c) 2010-2012,2017-2019 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
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25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Ron Dreslinski
45 #include "mem/abstract_mem.hh"
49 #include "arch/locked_mem.hh"
50 #include "cpu/base.hh"
51 #include "cpu/thread_context.hh"
52 #include "debug/LLSC.hh"
53 #include "debug/MemoryAccess.hh"
54 #include "mem/packet_access.hh"
55 #include "sim/system.hh"
59 AbstractMemory::AbstractMemory(const Params
*p
) :
60 ClockedObject(p
), range(params()->range
), pmemAddr(NULL
),
61 backdoor(params()->range
, nullptr,
62 (MemBackdoor::Flags
)(MemBackdoor::Readable
|
63 MemBackdoor::Writeable
)),
64 confTableReported(p
->conf_table_reported
), inAddrMap(p
->in_addr_map
),
65 kvmMap(p
->kvm_map
), _system(NULL
),
71 AbstractMemory::init()
75 if (size() % _system
->getPageBytes() != 0)
76 panic("Memory Size not divisible by page size\n");
80 AbstractMemory::setBackingStore(uint8_t* pmem_addr
)
82 // If there was an existing backdoor, let everybody know it's going away.
84 backdoor
.invalidate();
86 // The back door can't handle interleaved memory.
87 backdoor
.ptr(range
.interleaved() ? nullptr : pmem_addr
);
92 AbstractMemory::MemStats::MemStats(AbstractMemory
&_mem
)
93 : Stats::Group(&_mem
), mem(_mem
),
94 bytesRead(this, "bytes_read",
95 "Number of bytes read from this memory"),
96 bytesInstRead(this, "bytes_inst_read",
97 "Number of instructions bytes read from this memory"),
98 bytesWritten(this, "bytes_written",
99 "Number of bytes written to this memory"),
100 numReads(this, "num_reads",
101 "Number of read requests responded to by this memory"),
102 numWrites(this, "num_writes",
103 "Number of write requests responded to by this memory"),
104 numOther(this, "num_other",
105 "Number of other requests responded to by this memory"),
106 bwRead(this, "bw_read",
107 "Total read bandwidth from this memory (bytes/s)"),
108 bwInstRead(this, "bw_inst_read",
109 "Instruction read bandwidth from this memory (bytes/s)"),
110 bwWrite(this, "bw_write",
111 "Write bandwidth from this memory (bytes/s)"),
112 bwTotal(this, "bw_total",
113 "Total bandwidth to/from this memory (bytes/s)")
118 AbstractMemory::MemStats::regStats()
120 using namespace Stats
;
122 Stats::Group::regStats();
124 System
*sys
= mem
.system();
126 const auto max_masters
= sys
->maxMasters();
130 .flags(total
| nozero
| nonan
)
132 for (int i
= 0; i
< max_masters
; i
++) {
133 bytesRead
.subname(i
, sys
->getMasterName(i
));
138 .flags(total
| nozero
| nonan
)
140 for (int i
= 0; i
< max_masters
; i
++) {
141 bytesInstRead
.subname(i
, sys
->getMasterName(i
));
146 .flags(total
| nozero
| nonan
)
148 for (int i
= 0; i
< max_masters
; i
++) {
149 bytesWritten
.subname(i
, sys
->getMasterName(i
));
154 .flags(total
| nozero
| nonan
)
156 for (int i
= 0; i
< max_masters
; i
++) {
157 numReads
.subname(i
, sys
->getMasterName(i
));
162 .flags(total
| nozero
| nonan
)
164 for (int i
= 0; i
< max_masters
; i
++) {
165 numWrites
.subname(i
, sys
->getMasterName(i
));
170 .flags(total
| nozero
| nonan
)
172 for (int i
= 0; i
< max_masters
; i
++) {
173 numOther
.subname(i
, sys
->getMasterName(i
));
179 .flags(total
| nozero
| nonan
)
181 for (int i
= 0; i
< max_masters
; i
++) {
182 bwRead
.subname(i
, sys
->getMasterName(i
));
187 .prereq(bytesInstRead
)
188 .flags(total
| nozero
| nonan
)
190 for (int i
= 0; i
< max_masters
; i
++) {
191 bwInstRead
.subname(i
, sys
->getMasterName(i
));
196 .prereq(bytesWritten
)
197 .flags(total
| nozero
| nonan
)
199 for (int i
= 0; i
< max_masters
; i
++) {
200 bwWrite
.subname(i
, sys
->getMasterName(i
));
206 .flags(total
| nozero
| nonan
)
208 for (int i
= 0; i
< max_masters
; i
++) {
209 bwTotal
.subname(i
, sys
->getMasterName(i
));
212 bwRead
= bytesRead
/ simSeconds
;
213 bwInstRead
= bytesInstRead
/ simSeconds
;
214 bwWrite
= bytesWritten
/ simSeconds
;
215 bwTotal
= (bytesRead
+ bytesWritten
) / simSeconds
;
219 AbstractMemory::getAddrRange() const
224 // Add load-locked to tracking list. Should only be called if the
225 // operation is a load and the LLSC flag is set.
227 AbstractMemory::trackLoadLocked(PacketPtr pkt
)
229 const RequestPtr
&req
= pkt
->req
;
230 Addr paddr
= LockedAddr::mask(req
->getPaddr());
232 // first we check if we already have a locked addr for this
233 // xc. Since each xc only gets one, we just update the
234 // existing record with the new address.
235 list
<LockedAddr
>::iterator i
;
237 for (i
= lockedAddrList
.begin(); i
!= lockedAddrList
.end(); ++i
) {
238 if (i
->matchesContext(req
)) {
239 DPRINTF(LLSC
, "Modifying lock record: context %d addr %#x\n",
240 req
->contextId(), paddr
);
246 // no record for this xc: need to allocate a new one
247 DPRINTF(LLSC
, "Adding lock record: context %d addr %#x\n",
248 req
->contextId(), paddr
);
249 lockedAddrList
.push_front(LockedAddr(req
));
253 // Called on *writes* only... both regular stores and
254 // store-conditional operations. Check for conventional stores which
255 // conflict with locked addresses, and for success/failure of store
258 AbstractMemory::checkLockedAddrList(PacketPtr pkt
)
260 const RequestPtr
&req
= pkt
->req
;
261 Addr paddr
= LockedAddr::mask(req
->getPaddr());
262 bool isLLSC
= pkt
->isLLSC();
264 // Initialize return value. Non-conditional stores always
265 // succeed. Assume conditional stores will fail until proven
267 bool allowStore
= !isLLSC
;
269 // Iterate over list. Note that there could be multiple matching records,
270 // as more than one context could have done a load locked to this location.
271 // Only remove records when we succeed in finding a record for (xc, addr);
272 // then, remove all records with this address. Failed store-conditionals do
273 // not blow unrelated reservations.
274 list
<LockedAddr
>::iterator i
= lockedAddrList
.begin();
277 while (i
!= lockedAddrList
.end()) {
278 if (i
->addr
== paddr
&& i
->matchesContext(req
)) {
279 // it's a store conditional, and as far as the memory system can
280 // tell, the requesting context's lock is still valid.
281 DPRINTF(LLSC
, "StCond success: context %d addr %#x\n",
282 req
->contextId(), paddr
);
286 // If we didn't find a match, keep searching! Someone else may well
287 // have a reservation on this line here but we may find ours in just
291 req
->setExtraData(allowStore
? 1 : 0);
293 // LLSCs that succeeded AND non-LLSC stores both fall into here:
295 // We write address paddr. However, there may be several entries with a
296 // reservation on this address (for other contextIds) and they must all
298 i
= lockedAddrList
.begin();
299 while (i
!= lockedAddrList
.end()) {
300 if (i
->addr
== paddr
) {
301 DPRINTF(LLSC
, "Erasing lock record: context %d addr %#x\n",
302 i
->contextId
, paddr
);
303 ContextID owner_cid
= i
->contextId
;
304 assert(owner_cid
!= InvalidContextID
);
305 ContextID requester_cid
= req
->hasContextId() ?
308 if (owner_cid
!= requester_cid
) {
309 ThreadContext
* ctx
= system()->getThreadContext(owner_cid
);
310 TheISA::globalClearExclusive(ctx
);
312 i
= lockedAddrList
.erase(i
);
324 tracePacket(System
*sys
, const char *label
, PacketPtr pkt
)
326 int size
= pkt
->getSize();
327 #if THE_ISA != NULL_ISA
328 if (size
== 1 || size
== 2 || size
== 4 || size
== 8) {
329 DPRINTF(MemoryAccess
,"%s from %s of size %i on address %#x data "
330 "%#x %c\n", label
, sys
->getMasterName(pkt
->req
->masterId()),
331 size
, pkt
->getAddr(), pkt
->getUintX(TheISA::GuestByteOrder
),
332 pkt
->req
->isUncacheable() ? 'U' : 'C');
336 DPRINTF(MemoryAccess
, "%s from %s of size %i on address %#x %c\n",
337 label
, sys
->getMasterName(pkt
->req
->masterId()),
338 size
, pkt
->getAddr(), pkt
->req
->isUncacheable() ? 'U' : 'C');
339 DDUMP(MemoryAccess
, pkt
->getConstPtr
<uint8_t>(), pkt
->getSize());
342 # define TRACE_PACKET(A) tracePacket(system(), A, pkt)
344 # define TRACE_PACKET(A)
348 AbstractMemory::access(PacketPtr pkt
)
350 if (pkt
->cacheResponding()) {
351 DPRINTF(MemoryAccess
, "Cache responding to %#llx: not responding\n",
356 if (pkt
->cmd
== MemCmd::CleanEvict
|| pkt
->cmd
== MemCmd::WritebackClean
) {
357 DPRINTF(MemoryAccess
, "CleanEvict on 0x%x: not responding\n",
362 assert(pkt
->getAddrRange().isSubset(range
));
364 uint8_t *hostAddr
= pmemAddr
+ pkt
->getAddr() - range
.start();
366 if (pkt
->cmd
== MemCmd::SwapReq
) {
367 if (pkt
->isAtomicOp()) {
369 pkt
->setData(hostAddr
);
370 (*(pkt
->getAtomicOp()))(hostAddr
);
373 std::vector
<uint8_t> overwrite_val(pkt
->getSize());
374 uint64_t condition_val64
;
375 uint32_t condition_val32
;
377 panic_if(!pmemAddr
, "Swap only works if there is real memory " \
378 "(i.e. null=False)");
380 bool overwrite_mem
= true;
381 // keep a copy of our possible write value, and copy what is at the
382 // memory address into the packet
383 pkt
->writeData(&overwrite_val
[0]);
384 pkt
->setData(hostAddr
);
386 if (pkt
->req
->isCondSwap()) {
387 if (pkt
->getSize() == sizeof(uint64_t)) {
388 condition_val64
= pkt
->req
->getExtraData();
389 overwrite_mem
= !std::memcmp(&condition_val64
, hostAddr
,
391 } else if (pkt
->getSize() == sizeof(uint32_t)) {
392 condition_val32
= (uint32_t)pkt
->req
->getExtraData();
393 overwrite_mem
= !std::memcmp(&condition_val32
, hostAddr
,
396 panic("Invalid size for conditional read/write\n");
400 std::memcpy(hostAddr
, &overwrite_val
[0], pkt
->getSize());
402 assert(!pkt
->req
->isInstFetch());
403 TRACE_PACKET("Read/Write");
404 stats
.numOther
[pkt
->req
->masterId()]++;
406 } else if (pkt
->isRead()) {
407 assert(!pkt
->isWrite());
409 assert(!pkt
->fromCache());
410 // if the packet is not coming from a cache then we have
411 // to do the LL/SC tracking here
412 trackLoadLocked(pkt
);
415 pkt
->setData(hostAddr
);
417 TRACE_PACKET(pkt
->req
->isInstFetch() ? "IFetch" : "Read");
418 stats
.numReads
[pkt
->req
->masterId()]++;
419 stats
.bytesRead
[pkt
->req
->masterId()] += pkt
->getSize();
420 if (pkt
->req
->isInstFetch())
421 stats
.bytesInstRead
[pkt
->req
->masterId()] += pkt
->getSize();
422 } else if (pkt
->isInvalidate() || pkt
->isClean()) {
423 assert(!pkt
->isWrite());
424 // in a fastmem system invalidating and/or cleaning packets
425 // can be seen due to cache maintenance requests
427 // no need to do anything
428 } else if (pkt
->isWrite()) {
431 pkt
->writeData(hostAddr
);
432 DPRINTF(MemoryAccess
, "%s wrote %i bytes to address %x\n",
433 __func__
, pkt
->getSize(), pkt
->getAddr());
435 assert(!pkt
->req
->isInstFetch());
436 TRACE_PACKET("Write");
437 stats
.numWrites
[pkt
->req
->masterId()]++;
438 stats
.bytesWritten
[pkt
->req
->masterId()] += pkt
->getSize();
441 panic("Unexpected packet %s", pkt
->print());
444 if (pkt
->needsResponse()) {
450 AbstractMemory::functionalAccess(PacketPtr pkt
)
452 assert(pkt
->getAddrRange().isSubset(range
));
454 uint8_t *hostAddr
= pmemAddr
+ pkt
->getAddr() - range
.start();
458 pkt
->setData(hostAddr
);
460 TRACE_PACKET("Read");
462 } else if (pkt
->isWrite()) {
464 pkt
->writeData(hostAddr
);
466 TRACE_PACKET("Write");
468 } else if (pkt
->isPrint()) {
469 Packet::PrintReqState
*prs
=
470 dynamic_cast<Packet::PrintReqState
*>(pkt
->senderState
);
472 // Need to call printLabels() explicitly since we're not going
473 // through printObj().
475 // Right now we just print the single byte at the specified address.
476 ccprintf(prs
->os
, "%s%#x\n", prs
->curPrefix(), *hostAddr
);
478 panic("AbstractMemory: unimplemented functional command %s",