2 * Copyright (c) 2010-2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Ron Dreslinski
47 #include "cpu/base.hh"
48 #include "cpu/thread_context.hh"
49 #include "debug/LLSC.hh"
50 #include "debug/MemoryAccess.hh"
51 #include "mem/abstract_mem.hh"
52 #include "mem/packet_access.hh"
53 #include "sim/system.hh"
57 AbstractMemory::AbstractMemory(const Params
*p
) :
58 MemObject(p
), range(params()->range
), pmemAddr(NULL
),
59 confTableReported(p
->conf_table_reported
), inAddrMap(p
->in_addr_map
),
65 AbstractMemory::init()
69 if (size() % _system
->getPageBytes() != 0)
70 panic("Memory Size not divisible by page size\n");
74 AbstractMemory::setBackingStore(uint8_t* pmem_addr
)
80 AbstractMemory::regStats()
82 MemObject::regStats();
84 using namespace Stats
;
89 .init(system()->maxMasters())
90 .name(name() + ".bytes_read")
91 .desc("Number of bytes read from this memory")
92 .flags(total
| nozero
| nonan
)
94 for (int i
= 0; i
< system()->maxMasters(); i
++) {
95 bytesRead
.subname(i
, system()->getMasterName(i
));
98 .init(system()->maxMasters())
99 .name(name() + ".bytes_inst_read")
100 .desc("Number of instructions bytes read from this memory")
101 .flags(total
| nozero
| nonan
)
103 for (int i
= 0; i
< system()->maxMasters(); i
++) {
104 bytesInstRead
.subname(i
, system()->getMasterName(i
));
107 .init(system()->maxMasters())
108 .name(name() + ".bytes_written")
109 .desc("Number of bytes written to this memory")
110 .flags(total
| nozero
| nonan
)
112 for (int i
= 0; i
< system()->maxMasters(); i
++) {
113 bytesWritten
.subname(i
, system()->getMasterName(i
));
116 .init(system()->maxMasters())
117 .name(name() + ".num_reads")
118 .desc("Number of read requests responded to by this memory")
119 .flags(total
| nozero
| nonan
)
121 for (int i
= 0; i
< system()->maxMasters(); i
++) {
122 numReads
.subname(i
, system()->getMasterName(i
));
125 .init(system()->maxMasters())
126 .name(name() + ".num_writes")
127 .desc("Number of write requests responded to by this memory")
128 .flags(total
| nozero
| nonan
)
130 for (int i
= 0; i
< system()->maxMasters(); i
++) {
131 numWrites
.subname(i
, system()->getMasterName(i
));
134 .init(system()->maxMasters())
135 .name(name() + ".num_other")
136 .desc("Number of other requests responded to by this memory")
137 .flags(total
| nozero
| nonan
)
139 for (int i
= 0; i
< system()->maxMasters(); i
++) {
140 numOther
.subname(i
, system()->getMasterName(i
));
143 .name(name() + ".bw_read")
144 .desc("Total read bandwidth from this memory (bytes/s)")
147 .flags(total
| nozero
| nonan
)
149 for (int i
= 0; i
< system()->maxMasters(); i
++) {
150 bwRead
.subname(i
, system()->getMasterName(i
));
154 .name(name() + ".bw_inst_read")
155 .desc("Instruction read bandwidth from this memory (bytes/s)")
157 .prereq(bytesInstRead
)
158 .flags(total
| nozero
| nonan
)
160 for (int i
= 0; i
< system()->maxMasters(); i
++) {
161 bwInstRead
.subname(i
, system()->getMasterName(i
));
164 .name(name() + ".bw_write")
165 .desc("Write bandwidth from this memory (bytes/s)")
167 .prereq(bytesWritten
)
168 .flags(total
| nozero
| nonan
)
170 for (int i
= 0; i
< system()->maxMasters(); i
++) {
171 bwWrite
.subname(i
, system()->getMasterName(i
));
174 .name(name() + ".bw_total")
175 .desc("Total bandwidth to/from this memory (bytes/s)")
178 .flags(total
| nozero
| nonan
)
180 for (int i
= 0; i
< system()->maxMasters(); i
++) {
181 bwTotal
.subname(i
, system()->getMasterName(i
));
183 bwRead
= bytesRead
/ simSeconds
;
184 bwInstRead
= bytesInstRead
/ simSeconds
;
185 bwWrite
= bytesWritten
/ simSeconds
;
186 bwTotal
= (bytesRead
+ bytesWritten
) / simSeconds
;
190 AbstractMemory::getAddrRange() const
195 // Add load-locked to tracking list. Should only be called if the
196 // operation is a load and the LLSC flag is set.
198 AbstractMemory::trackLoadLocked(PacketPtr pkt
)
200 Request
*req
= pkt
->req
;
201 Addr paddr
= LockedAddr::mask(req
->getPaddr());
203 // first we check if we already have a locked addr for this
204 // xc. Since each xc only gets one, we just update the
205 // existing record with the new address.
206 list
<LockedAddr
>::iterator i
;
208 for (i
= lockedAddrList
.begin(); i
!= lockedAddrList
.end(); ++i
) {
209 if (i
->matchesContext(req
)) {
210 DPRINTF(LLSC
, "Modifying lock record: context %d addr %#x\n",
211 req
->contextId(), paddr
);
217 // no record for this xc: need to allocate a new one
218 DPRINTF(LLSC
, "Adding lock record: context %d addr %#x\n",
219 req
->contextId(), paddr
);
220 lockedAddrList
.push_front(LockedAddr(req
));
224 // Called on *writes* only... both regular stores and
225 // store-conditional operations. Check for conventional stores which
226 // conflict with locked addresses, and for success/failure of store
229 AbstractMemory::checkLockedAddrList(PacketPtr pkt
)
231 Request
*req
= pkt
->req
;
232 Addr paddr
= LockedAddr::mask(req
->getPaddr());
233 bool isLLSC
= pkt
->isLLSC();
235 // Initialize return value. Non-conditional stores always
236 // succeed. Assume conditional stores will fail until proven
238 bool allowStore
= !isLLSC
;
240 // Iterate over list. Note that there could be multiple matching records,
241 // as more than one context could have done a load locked to this location.
242 // Only remove records when we succeed in finding a record for (xc, addr);
243 // then, remove all records with this address. Failed store-conditionals do
244 // not blow unrelated reservations.
245 list
<LockedAddr
>::iterator i
= lockedAddrList
.begin();
248 while (i
!= lockedAddrList
.end()) {
249 if (i
->addr
== paddr
&& i
->matchesContext(req
)) {
250 // it's a store conditional, and as far as the memory system can
251 // tell, the requesting context's lock is still valid.
252 DPRINTF(LLSC
, "StCond success: context %d addr %#x\n",
253 req
->contextId(), paddr
);
257 // If we didn't find a match, keep searching! Someone else may well
258 // have a reservation on this line here but we may find ours in just
262 req
->setExtraData(allowStore
? 1 : 0);
264 // LLSCs that succeeded AND non-LLSC stores both fall into here:
266 // We write address paddr. However, there may be several entries with a
267 // reservation on this address (for other contextIds) and they must all
269 i
= lockedAddrList
.begin();
270 while (i
!= lockedAddrList
.end()) {
271 if (i
->addr
== paddr
) {
272 DPRINTF(LLSC
, "Erasing lock record: context %d addr %#x\n",
273 i
->contextId
, paddr
);
274 // For ARM, a spinlock would typically include a Wait
275 // For Event (WFE) to conserve energy. The ARMv8
276 // architecture specifies that an event is
277 // automatically generated when clearing the exclusive
278 // monitor to wake up the processor in WFE.
279 ThreadContext
* ctx
= system()->getThreadContext(i
->contextId
);
280 ctx
->getCpuPtr()->wakeup(ctx
->threadId());
281 i
= lockedAddrList
.erase(i
);
296 DPRINTF(MemoryAccess,"%s from %s of size %i on address 0x%x data " \
297 "0x%x %c\n", A, system()->getMasterName(pkt->req->masterId()),\
298 pkt->getSize(), pkt->getAddr(), pkt->get<T>(), \
299 pkt->req->isUncacheable() ? 'U' : 'C'); \
303 #define TRACE_PACKET(A) \
305 switch (pkt->getSize()) { \
311 DPRINTF(MemoryAccess, "%s from %s of size %i on address 0x%x %c\n",\
312 A, system()->getMasterName(pkt->req->masterId()), \
313 pkt->getSize(), pkt->getAddr(), \
314 pkt->req->isUncacheable() ? 'U' : 'C'); \
315 DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize()); \
321 #define TRACE_PACKET(A)
326 AbstractMemory::access(PacketPtr pkt
)
328 if (pkt
->cacheResponding()) {
329 DPRINTF(MemoryAccess
, "Cache responding to %#llx: not responding\n",
334 if (pkt
->cmd
== MemCmd::CleanEvict
|| pkt
->cmd
== MemCmd::WritebackClean
) {
335 DPRINTF(MemoryAccess
, "CleanEvict on 0x%x: not responding\n",
340 assert(AddrRange(pkt
->getAddr(),
341 pkt
->getAddr() + (pkt
->getSize() - 1)).isSubset(range
));
343 uint8_t *hostAddr
= pmemAddr
+ pkt
->getAddr() - range
.start();
345 if (pkt
->cmd
== MemCmd::SwapReq
) {
346 if (pkt
->isAtomicOp()) {
348 memcpy(pkt
->getPtr
<uint8_t>(), hostAddr
, pkt
->getSize());
349 (*(pkt
->getAtomicOp()))(hostAddr
);
352 std::vector
<uint8_t> overwrite_val(pkt
->getSize());
353 uint64_t condition_val64
;
354 uint32_t condition_val32
;
357 panic("Swap only works if there is real memory (i.e. null=False)");
359 bool overwrite_mem
= true;
360 // keep a copy of our possible write value, and copy what is at the
361 // memory address into the packet
362 std::memcpy(&overwrite_val
[0], pkt
->getConstPtr
<uint8_t>(),
364 std::memcpy(pkt
->getPtr
<uint8_t>(), hostAddr
, pkt
->getSize());
366 if (pkt
->req
->isCondSwap()) {
367 if (pkt
->getSize() == sizeof(uint64_t)) {
368 condition_val64
= pkt
->req
->getExtraData();
369 overwrite_mem
= !std::memcmp(&condition_val64
, hostAddr
,
371 } else if (pkt
->getSize() == sizeof(uint32_t)) {
372 condition_val32
= (uint32_t)pkt
->req
->getExtraData();
373 overwrite_mem
= !std::memcmp(&condition_val32
, hostAddr
,
376 panic("Invalid size for conditional read/write\n");
380 std::memcpy(hostAddr
, &overwrite_val
[0], pkt
->getSize());
382 assert(!pkt
->req
->isInstFetch());
383 TRACE_PACKET("Read/Write");
384 numOther
[pkt
->req
->masterId()]++;
386 } else if (pkt
->isRead()) {
387 assert(!pkt
->isWrite());
389 trackLoadLocked(pkt
);
392 memcpy(pkt
->getPtr
<uint8_t>(), hostAddr
, pkt
->getSize());
393 TRACE_PACKET(pkt
->req
->isInstFetch() ? "IFetch" : "Read");
394 numReads
[pkt
->req
->masterId()]++;
395 bytesRead
[pkt
->req
->masterId()] += pkt
->getSize();
396 if (pkt
->req
->isInstFetch())
397 bytesInstRead
[pkt
->req
->masterId()] += pkt
->getSize();
398 } else if (pkt
->isInvalidate()) {
399 // no need to do anything
400 // this clause is intentionally before the write clause: the only
401 // transaction that is both a write and an invalidate is
402 // WriteInvalidate, and for the sake of consistency, it does not
403 // write to memory. in a cacheless system, there are no WriteInv's
404 // because the Write -> WriteInvalidate rewrite happens in the cache.
405 } else if (pkt
->isWrite()) {
408 memcpy(hostAddr
, pkt
->getConstPtr
<uint8_t>(), pkt
->getSize());
409 DPRINTF(MemoryAccess
, "%s wrote %x bytes to address %x\n",
410 __func__
, pkt
->getSize(), pkt
->getAddr());
412 assert(!pkt
->req
->isInstFetch());
413 TRACE_PACKET("Write");
414 numWrites
[pkt
->req
->masterId()]++;
415 bytesWritten
[pkt
->req
->masterId()] += pkt
->getSize();
418 panic("unimplemented");
421 if (pkt
->needsResponse()) {
427 AbstractMemory::functionalAccess(PacketPtr pkt
)
429 assert(AddrRange(pkt
->getAddr(),
430 pkt
->getAddr() + pkt
->getSize() - 1).isSubset(range
));
432 uint8_t *hostAddr
= pmemAddr
+ pkt
->getAddr() - range
.start();
436 memcpy(pkt
->getPtr
<uint8_t>(), hostAddr
, pkt
->getSize());
437 TRACE_PACKET("Read");
439 } else if (pkt
->isWrite()) {
441 memcpy(hostAddr
, pkt
->getConstPtr
<uint8_t>(), pkt
->getSize());
442 TRACE_PACKET("Write");
444 } else if (pkt
->isPrint()) {
445 Packet::PrintReqState
*prs
=
446 dynamic_cast<Packet::PrintReqState
*>(pkt
->senderState
);
448 // Need to call printLabels() explicitly since we're not going
449 // through printObj().
451 // Right now we just print the single byte at the specified address.
452 ccprintf(prs
->os
, "%s%#x\n", prs
->curPrefix(), *hostAddr
);
454 panic("AbstractMemory: unimplemented functional command %s",