src/mem/abstract_mem.cc

   1 /*
   2  * Copyright (c) 2010-2012,2017-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
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  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #include "mem/abstract_mem.hh"
  42
  43 #include <vector>
  44
  45 #include "arch/locked_mem.hh"
  46 #include "base/loader/memory_image.hh"
  47 #include "base/loader/object_file.hh"
  48 #include "cpu/thread_context.hh"
  49 #include "debug/LLSC.hh"
  50 #include "debug/MemoryAccess.hh"
  51 #include "mem/packet_access.hh"
  52 #include "sim/system.hh"
  53
  54 using namespace std;
  55
  56 AbstractMemory::AbstractMemory(const Params &p) :
  57     ClockedObject(p), range(p.range), pmemAddr(NULL),
  58     backdoor(params().range, nullptr,
  59              (MemBackdoor::Flags)(MemBackdoor::Readable |
  60                                   MemBackdoor::Writeable)),
  61     confTableReported(p.conf_table_reported), inAddrMap(p.in_addr_map),
  62     kvmMap(p.kvm_map), _system(NULL),
  63     stats(*this)
  64 {
  65     panic_if(!range.valid() || !range.size(),
  66              "Memory range %s must be valid with non-zero size.",
  67              range.to_string());
  68 }
  69
  70 void
  71 AbstractMemory::initState()
  72 {
  73     ClockedObject::initState();
  74
  75     const auto &file = params().image_file;
  76     if (file == "")
  77         return;
  78
  79     auto *object = Loader::createObjectFile(file, true);
  80     fatal_if(!object, "%s: Could not load %s.", name(), file);
  81
  82     Loader::debugSymbolTable.insert(*object->symtab().globals());
  83     Loader::MemoryImage image = object->buildImage();
  84
  85     AddrRange image_range(image.minAddr(), image.maxAddr());
  86     if (!range.contains(image_range.start())) {
  87         warn("%s: Moving image from %s to memory address range %s.",
  88                 name(), image_range.to_string(), range.to_string());
  89         image = image.offset(range.start());
  90         image_range = AddrRange(image.minAddr(), image.maxAddr());
  91     }
  92     panic_if(!image_range.isSubset(range), "%s: memory image %s doesn't fit.",
  93              name(), file);
  94
  95     PortProxy proxy([this](PacketPtr pkt) { functionalAccess(pkt); },
  96                     system()->cacheLineSize());
  97
  98     panic_if(!image.write(proxy), "%s: Unable to write image.");
  99 }
 100
 101 void
 102 AbstractMemory::setBackingStore(uint8_t* pmem_addr)
 103 {
 104     // If there was an existing backdoor, let everybody know it's going away.
 105     if (backdoor.ptr())
 106         backdoor.invalidate();
 107
 108     // The back door can't handle interleaved memory.
 109     backdoor.ptr(range.interleaved() ? nullptr : pmem_addr);
 110
 111     pmemAddr = pmem_addr;
 112 }
 113
 114 AbstractMemory::MemStats::MemStats(AbstractMemory &_mem)
 115     : Stats::Group(&_mem), mem(_mem),
 116     bytesRead(this, "bytes_read",
 117               "Number of bytes read from this memory"),
 118     bytesInstRead(this, "bytes_inst_read",
 119                   "Number of instructions bytes read from this memory"),
 120     bytesWritten(this, "bytes_written",
 121                  "Number of bytes written to this memory"),
 122     numReads(this, "num_reads",
 123              "Number of read requests responded to by this memory"),
 124     numWrites(this, "num_writes",
 125               "Number of write requests responded to by this memory"),
 126     numOther(this, "num_other",
 127              "Number of other requests responded to by this memory"),
 128     bwRead(this, "bw_read",
 129            "Total read bandwidth from this memory (bytes/s)"),
 130     bwInstRead(this, "bw_inst_read",
 131                "Instruction read bandwidth from this memory (bytes/s)"),
 132     bwWrite(this, "bw_write",
 133             "Write bandwidth from this memory (bytes/s)"),
 134     bwTotal(this, "bw_total",
 135             "Total bandwidth to/from this memory (bytes/s)")
 136 {
 137 }
 138
 139 void
 140 AbstractMemory::MemStats::regStats()
 141 {
 142     using namespace Stats;
 143
 144     Stats::Group::regStats();
 145
 146     System *sys = mem.system();
 147     assert(sys);
 148     const auto max_requestors = sys->maxRequestors();
 149
 150     bytesRead
 151         .init(max_requestors)
 152         .flags(total | nozero | nonan)
 153         ;
 154     for (int i = 0; i < max_requestors; i++) {
 155         bytesRead.subname(i, sys->getRequestorName(i));
 156     }
 157
 158     bytesInstRead
 159         .init(max_requestors)
 160         .flags(total | nozero | nonan)
 161         ;
 162     for (int i = 0; i < max_requestors; i++) {
 163         bytesInstRead.subname(i, sys->getRequestorName(i));
 164     }
 165
 166     bytesWritten
 167         .init(max_requestors)
 168         .flags(total | nozero | nonan)
 169         ;
 170     for (int i = 0; i < max_requestors; i++) {
 171         bytesWritten.subname(i, sys->getRequestorName(i));
 172     }
 173
 174     numReads
 175         .init(max_requestors)
 176         .flags(total | nozero | nonan)
 177         ;
 178     for (int i = 0; i < max_requestors; i++) {
 179         numReads.subname(i, sys->getRequestorName(i));
 180     }
 181
 182     numWrites
 183         .init(max_requestors)
 184         .flags(total | nozero | nonan)
 185         ;
 186     for (int i = 0; i < max_requestors; i++) {
 187         numWrites.subname(i, sys->getRequestorName(i));
 188     }
 189
 190     numOther
 191         .init(max_requestors)
 192         .flags(total | nozero | nonan)
 193         ;
 194     for (int i = 0; i < max_requestors; i++) {
 195         numOther.subname(i, sys->getRequestorName(i));
 196     }
 197
 198     bwRead
 199         .precision(0)
 200         .prereq(bytesRead)
 201         .flags(total | nozero | nonan)
 202         ;
 203     for (int i = 0; i < max_requestors; i++) {
 204         bwRead.subname(i, sys->getRequestorName(i));
 205     }
 206
 207     bwInstRead
 208         .precision(0)
 209         .prereq(bytesInstRead)
 210         .flags(total | nozero | nonan)
 211         ;
 212     for (int i = 0; i < max_requestors; i++) {
 213         bwInstRead.subname(i, sys->getRequestorName(i));
 214     }
 215
 216     bwWrite
 217         .precision(0)
 218         .prereq(bytesWritten)
 219         .flags(total | nozero | nonan)
 220         ;
 221     for (int i = 0; i < max_requestors; i++) {
 222         bwWrite.subname(i, sys->getRequestorName(i));
 223     }
 224
 225     bwTotal
 226         .precision(0)
 227         .prereq(bwTotal)
 228         .flags(total | nozero | nonan)
 229         ;
 230     for (int i = 0; i < max_requestors; i++) {
 231         bwTotal.subname(i, sys->getRequestorName(i));
 232     }
 233
 234     bwRead = bytesRead / simSeconds;
 235     bwInstRead = bytesInstRead / simSeconds;
 236     bwWrite = bytesWritten / simSeconds;
 237     bwTotal = (bytesRead + bytesWritten) / simSeconds;
 238 }
 239
 240 AddrRange
 241 AbstractMemory::getAddrRange() const
 242 {
 243     return range;
 244 }
 245
 246 // Add load-locked to tracking list.  Should only be called if the
 247 // operation is a load and the LLSC flag is set.
 248 void
 249 AbstractMemory::trackLoadLocked(PacketPtr pkt)
 250 {
 251     const RequestPtr &req = pkt->req;
 252     Addr paddr = LockedAddr::mask(req->getPaddr());
 253
 254     // first we check if we already have a locked addr for this
 255     // xc.  Since each xc only gets one, we just update the
 256     // existing record with the new address.
 257     list<LockedAddr>::iterator i;
 258
 259     for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
 260         if (i->matchesContext(req)) {
 261             DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n",
 262                     req->contextId(), paddr);
 263             i->addr = paddr;
 264             return;
 265         }
 266     }
 267
 268     // no record for this xc: need to allocate a new one
 269     DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
 270             req->contextId(), paddr);
 271     lockedAddrList.push_front(LockedAddr(req));
 272     backdoor.invalidate();
 273 }
 274
 275
 276 // Called on *writes* only... both regular stores and
 277 // store-conditional operations.  Check for conventional stores which
 278 // conflict with locked addresses, and for success/failure of store
 279 // conditionals.
 280 bool
 281 AbstractMemory::checkLockedAddrList(PacketPtr pkt)
 282 {
 283     const RequestPtr &req = pkt->req;
 284     Addr paddr = LockedAddr::mask(req->getPaddr());
 285     bool isLLSC = pkt->isLLSC();
 286
 287     // Initialize return value.  Non-conditional stores always
 288     // succeed.  Assume conditional stores will fail until proven
 289     // otherwise.
 290     bool allowStore = !isLLSC;
 291
 292     // Iterate over list.  Note that there could be multiple matching records,
 293     // as more than one context could have done a load locked to this location.
 294     // Only remove records when we succeed in finding a record for (xc, addr);
 295     // then, remove all records with this address.  Failed store-conditionals do
 296     // not blow unrelated reservations.
 297     list<LockedAddr>::iterator i = lockedAddrList.begin();
 298
 299     if (isLLSC) {
 300         while (i != lockedAddrList.end()) {
 301             if (i->addr == paddr && i->matchesContext(req)) {
 302                 // it's a store conditional, and as far as the memory system can
 303                 // tell, the requesting context's lock is still valid.
 304                 DPRINTF(LLSC, "StCond success: context %d addr %#x\n",
 305                         req->contextId(), paddr);
 306                 allowStore = true;
 307                 break;
 308             }
 309             // If we didn't find a match, keep searching!  Someone else may well
 310             // have a reservation on this line here but we may find ours in just
 311             // a little while.
 312             i++;
 313         }
 314         req->setExtraData(allowStore ? 1 : 0);
 315     }
 316     // LLSCs that succeeded AND non-LLSC stores both fall into here:
 317     if (allowStore) {
 318         // We write address paddr.  However, there may be several entries with a
 319         // reservation on this address (for other contextIds) and they must all
 320         // be removed.
 321         i = lockedAddrList.begin();
 322         while (i != lockedAddrList.end()) {
 323             if (i->addr == paddr) {
 324                 DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
 325                         i->contextId, paddr);
 326                 ContextID owner_cid = i->contextId;
 327                 assert(owner_cid != InvalidContextID);
 328                 ContextID requestor_cid = req->hasContextId() ?
 329                                            req->contextId() :
 330                                            InvalidContextID;
 331                 if (owner_cid != requestor_cid) {
 332                     ThreadContext* ctx = system()->threads[owner_cid];
 333                     TheISA::globalClearExclusive(ctx);
 334                 }
 335                 i = lockedAddrList.erase(i);
 336             } else {
 337                 i++;
 338             }
 339         }
 340     }
 341
 342     return allowStore;
 343 }
 344
 345 #if TRACING_ON
 346 static inline void
 347 tracePacket(System *sys, const char *label, PacketPtr pkt)
 348 {
 349     int size = pkt->getSize();
 350     if (size == 1 || size == 2 || size == 4 || size == 8) {
 351         ByteOrder byte_order = sys->getGuestByteOrder();
 352         DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x data "
 353                 "%#x %c\n", label, sys->getRequestorName(pkt->req->
 354                 requestorId()), size, pkt->getAddr(),
 355                 size, pkt->getAddr(), pkt->getUintX(byte_order),
 356                 pkt->req->isUncacheable() ? 'U' : 'C');
 357         return;
 358     }
 359     DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x %c\n",
 360             label, sys->getRequestorName(pkt->req->requestorId()),
 361             size, pkt->getAddr(), pkt->req->isUncacheable() ? 'U' : 'C');
 362     DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize());
 363 }
 364
 365 #   define TRACE_PACKET(A) tracePacket(system(), A, pkt)
 366 #else
 367 #   define TRACE_PACKET(A)
 368 #endif
 369
 370 void
 371 AbstractMemory::access(PacketPtr pkt)
 372 {
 373     if (pkt->cacheResponding()) {
 374         DPRINTF(MemoryAccess, "Cache responding to %#llx: not responding\n",
 375                 pkt->getAddr());
 376         return;
 377     }
 378
 379     if (pkt->cmd == MemCmd::CleanEvict || pkt->cmd == MemCmd::WritebackClean) {
 380         DPRINTF(MemoryAccess, "CleanEvict  on 0x%x: not responding\n",
 381                 pkt->getAddr());
 382       return;
 383     }
 384
 385     assert(pkt->getAddrRange().isSubset(range));
 386
 387     uint8_t *host_addr = toHostAddr(pkt->getAddr());
 388
 389     if (pkt->cmd == MemCmd::SwapReq) {
 390         if (pkt->isAtomicOp()) {
 391             if (pmemAddr) {
 392                 pkt->setData(host_addr);
 393                 (*(pkt->getAtomicOp()))(host_addr);
 394             }
 395         } else {
 396             std::vector<uint8_t> overwrite_val(pkt->getSize());
 397             uint64_t condition_val64;
 398             uint32_t condition_val32;
 399
 400             panic_if(!pmemAddr, "Swap only works if there is real memory " \
 401                      "(i.e. null=False)");
 402
 403             bool overwrite_mem = true;
 404             // keep a copy of our possible write value, and copy what is at the
 405             // memory address into the packet
 406             pkt->writeData(&overwrite_val[0]);
 407             pkt->setData(host_addr);
 408
 409             if (pkt->req->isCondSwap()) {
 410                 if (pkt->getSize() == sizeof(uint64_t)) {
 411                     condition_val64 = pkt->req->getExtraData();
 412                     overwrite_mem = !std::memcmp(&condition_val64, host_addr,
 413                                                  sizeof(uint64_t));
 414                 } else if (pkt->getSize() == sizeof(uint32_t)) {
 415                     condition_val32 = (uint32_t)pkt->req->getExtraData();
 416                     overwrite_mem = !std::memcmp(&condition_val32, host_addr,
 417                                                  sizeof(uint32_t));
 418                 } else
 419                     panic("Invalid size for conditional read/write\n");
 420             }
 421
 422             if (overwrite_mem)
 423                 std::memcpy(host_addr, &overwrite_val[0], pkt->getSize());
 424
 425             assert(!pkt->req->isInstFetch());
 426             TRACE_PACKET("Read/Write");
 427             stats.numOther[pkt->req->requestorId()]++;
 428         }
 429     } else if (pkt->isRead()) {
 430         assert(!pkt->isWrite());
 431         if (pkt->isLLSC()) {
 432             assert(!pkt->fromCache());
 433             // if the packet is not coming from a cache then we have
 434             // to do the LL/SC tracking here
 435             trackLoadLocked(pkt);
 436         }
 437         if (pmemAddr) {
 438             pkt->setData(host_addr);
 439         }
 440         TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
 441         stats.numReads[pkt->req->requestorId()]++;
 442         stats.bytesRead[pkt->req->requestorId()] += pkt->getSize();
 443         if (pkt->req->isInstFetch())
 444             stats.bytesInstRead[pkt->req->requestorId()] += pkt->getSize();
 445     } else if (pkt->isInvalidate() || pkt->isClean()) {
 446         assert(!pkt->isWrite());
 447         // in a fastmem system invalidating and/or cleaning packets
 448         // can be seen due to cache maintenance requests
 449
 450         // no need to do anything
 451     } else if (pkt->isWrite()) {
 452         if (writeOK(pkt)) {
 453             if (pmemAddr) {
 454                 pkt->writeData(host_addr);
 455                 DPRINTF(MemoryAccess, "%s write due to %s\n",
 456                         __func__, pkt->print());
 457             }
 458             assert(!pkt->req->isInstFetch());
 459             TRACE_PACKET("Write");
 460             stats.numWrites[pkt->req->requestorId()]++;
 461             stats.bytesWritten[pkt->req->requestorId()] += pkt->getSize();
 462         }
 463     } else {
 464         panic("Unexpected packet %s", pkt->print());
 465     }
 466
 467     if (pkt->needsResponse()) {
 468         pkt->makeResponse();
 469     }
 470 }
 471
 472 void
 473 AbstractMemory::functionalAccess(PacketPtr pkt)
 474 {
 475     assert(pkt->getAddrRange().isSubset(range));
 476
 477     uint8_t *host_addr = toHostAddr(pkt->getAddr());
 478
 479     if (pkt->isRead()) {
 480         if (pmemAddr) {
 481             pkt->setData(host_addr);
 482         }
 483         TRACE_PACKET("Read");
 484         pkt->makeResponse();
 485     } else if (pkt->isWrite()) {
 486         if (pmemAddr) {
 487             pkt->writeData(host_addr);
 488         }
 489         TRACE_PACKET("Write");
 490         pkt->makeResponse();
 491     } else if (pkt->isPrint()) {
 492         Packet::PrintReqState *prs =
 493             dynamic_cast<Packet::PrintReqState*>(pkt->senderState);
 494         assert(prs);
 495         // Need to call printLabels() explicitly since we're not going
 496         // through printObj().
 497         prs->printLabels();
 498         // Right now we just print the single byte at the specified address.
 499         ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *host_addr);
 500     } else {
 501         panic("AbstractMemory: unimplemented functional command %s",
 502               pkt->cmdString());
 503     }
 504 }