src/mem/bridge.hh

   1 /*
   2  * Copyright (c) 2011-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  *          Steve Reinhardt
  42  *          Andreas Hansson
  43  */
  44
  45 /**
  46  * @file
  47  * Declaration of a memory-mapped bridge that connects a master
  48  * and a slave through a request and response queue.
  49  */
  50
  51 #ifndef __MEM_BRIDGE_HH__
  52 #define __MEM_BRIDGE_HH__
  53
  54 #include <deque>
  55
  56 #include "base/types.hh"
  57 #include "mem/mem_object.hh"
  58 #include "params/Bridge.hh"
  59
  60 /**
  61  * A bridge is used to interface two different crossbars (or in general a
  62  * memory-mapped master and slave), with buffering for requests and
  63  * responses. The bridge has a fixed delay for packets passing through
  64  * it and responds to a fixed set of address ranges.
  65  *
  66  * The bridge comprises a slave port and a master port, that buffer
  67  * outgoing responses and requests respectively. Buffer space is
  68  * reserved when a request arrives, also reserving response space
  69  * before forwarding the request. If there is no space present, then
  70  * the bridge will delay accepting the packet until space becomes
  71  * available.
  72  */
  73 class Bridge : public MemObject
  74 {
  75   protected:
  76
  77     /**
  78      * A bridge request state stores packets along with their sender
  79      * state and original source. It has enough information to also
  80      * restore the response once it comes back to the bridge.
  81      */
  82     class RequestState : public Packet::SenderState
  83     {
  84
  85       public:
  86
  87         const PortID origSrc;
  88
  89         RequestState(PortID orig_src) : origSrc(orig_src)
  90         { }
  91
  92     };
  93
  94     /**
  95      * A deferred packet stores a packet along with its scheduled
  96      * transmission time
  97      */
  98     class DeferredPacket
  99     {
 100
 101       public:
 102
 103         const Tick tick;
 104         const PacketPtr pkt;
 105
 106         DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
 107         { }
 108     };
 109
 110     // Forward declaration to allow the slave port to have a pointer
 111     class BridgeMasterPort;
 112
 113     /**
 114      * The port on the side that receives requests and sends
 115      * responses. The slave port has a set of address ranges that it
 116      * is responsible for. The slave port also has a buffer for the
 117      * responses not yet sent.
 118      */
 119     class BridgeSlavePort : public SlavePort
 120     {
 121
 122       private:
 123
 124         /** The bridge to which this port belongs. */
 125         Bridge& bridge;
 126
 127         /**
 128          * Master port on the other side of the bridge.
 129          */
 130         BridgeMasterPort& masterPort;
 131
 132         /** Minimum request delay though this bridge. */
 133         const Cycles delay;
 134
 135         /** Address ranges to pass through the bridge */
 136         const AddrRangeList ranges;
 137
 138         /**
 139          * Response packet queue. Response packets are held in this
 140          * queue for a specified delay to model the processing delay
 141          * of the bridge. We use a deque as we need to iterate over
 142          * the items for functional accesses.
 143          */
 144         std::deque<DeferredPacket> transmitList;
 145
 146         /** Counter to track the outstanding responses. */
 147         unsigned int outstandingResponses;
 148
 149         /** If we should send a retry when space becomes available. */
 150         bool retryReq;
 151
 152         /** Max queue size for reserved responses. */
 153         unsigned int respQueueLimit;
 154
 155         /**
 156          * Is this side blocked from accepting new response packets.
 157          *
 158          * @return true if the reserved space has reached the set limit
 159          */
 160         bool respQueueFull() const;
 161
 162         /**
 163          * Handle send event, scheduled when the packet at the head of
 164          * the response queue is ready to transmit (for timing
 165          * accesses only).
 166          */
 167         void trySendTiming();
 168
 169         /** Send event for the response queue. */
 170         EventWrapper<BridgeSlavePort,
 171                      &BridgeSlavePort::trySendTiming> sendEvent;
 172
 173       public:
 174
 175         /**
 176          * Constructor for the BridgeSlavePort.
 177          *
 178          * @param _name the port name including the owner
 179          * @param _bridge the structural owner
 180          * @param _masterPort the master port on the other side of the bridge
 181          * @param _delay the delay in cycles from receiving to sending
 182          * @param _resp_limit the size of the response queue
 183          * @param _ranges a number of address ranges to forward
 184          */
 185         BridgeSlavePort(const std::string& _name, Bridge& _bridge,
 186                         BridgeMasterPort& _masterPort, Cycles _delay,
 187                         int _resp_limit, std::vector<AddrRange> _ranges);
 188
 189         /**
 190          * Queue a response packet to be sent out later and also schedule
 191          * a send if necessary.
 192          *
 193          * @param pkt a response to send out after a delay
 194          * @param when tick when response packet should be sent
 195          */
 196         void schedTimingResp(PacketPtr pkt, Tick when);
 197
 198         /**
 199          * Retry any stalled request that we have failed to accept at
 200          * an earlier point in time. This call will do nothing if no
 201          * request is waiting.
 202          */
 203         void retryStalledReq();
 204
 205       protected:
 206
 207         /** When receiving a timing request from the peer port,
 208             pass it to the bridge. */
 209         bool recvTimingReq(PacketPtr pkt);
 210
 211         /** When receiving a retry request from the peer port,
 212             pass it to the bridge. */
 213         void recvRetry();
 214
 215         /** When receiving a Atomic requestfrom the peer port,
 216             pass it to the bridge. */
 217         Tick recvAtomic(PacketPtr pkt);
 218
 219         /** When receiving a Functional request from the peer port,
 220             pass it to the bridge. */
 221         void recvFunctional(PacketPtr pkt);
 222
 223         /** When receiving a address range request the peer port,
 224             pass it to the bridge. */
 225         AddrRangeList getAddrRanges() const;
 226     };
 227
 228
 229     /**
 230      * Port on the side that forwards requests and receives
 231      * responses. The master port has a buffer for the requests not
 232      * yet sent.
 233      */
 234     class BridgeMasterPort : public MasterPort
 235     {
 236
 237       private:
 238
 239         /** The bridge to which this port belongs. */
 240         Bridge& bridge;
 241
 242         /**
 243          * The slave port on the other side of the bridge.
 244          */
 245         BridgeSlavePort& slavePort;
 246
 247         /** Minimum delay though this bridge. */
 248         const Cycles delay;
 249
 250         /**
 251          * Request packet queue. Request packets are held in this
 252          * queue for a specified delay to model the processing delay
 253          * of the bridge.  We use a deque as we need to iterate over
 254          * the items for functional accesses.
 255          */
 256         std::deque<DeferredPacket> transmitList;
 257
 258         /** Max queue size for request packets */
 259         const unsigned int reqQueueLimit;
 260
 261         /**
 262          * Handle send event, scheduled when the packet at the head of
 263          * the outbound queue is ready to transmit (for timing
 264          * accesses only).
 265          */
 266         void trySendTiming();
 267
 268         /** Send event for the request queue. */
 269         EventWrapper<BridgeMasterPort,
 270                      &BridgeMasterPort::trySendTiming> sendEvent;
 271
 272       public:
 273
 274         /**
 275          * Constructor for the BridgeMasterPort.
 276          *
 277          * @param _name the port name including the owner
 278          * @param _bridge the structural owner
 279          * @param _slavePort the slave port on the other side of the bridge
 280          * @param _delay the delay in cycles from receiving to sending
 281          * @param _req_limit the size of the request queue
 282          */
 283         BridgeMasterPort(const std::string& _name, Bridge& _bridge,
 284                          BridgeSlavePort& _slavePort, Cycles _delay,
 285                          int _req_limit);
 286
 287         /**
 288          * Is this side blocked from accepting new request packets.
 289          *
 290          * @return true if the occupied space has reached the set limit
 291          */
 292         bool reqQueueFull() const;
 293
 294         /**
 295          * Queue a request packet to be sent out later and also schedule
 296          * a send if necessary.
 297          *
 298          * @param pkt a request to send out after a delay
 299          * @param when tick when response packet should be sent
 300          */
 301         void schedTimingReq(PacketPtr pkt, Tick when);
 302
 303         /**
 304          * Check a functional request against the packets in our
 305          * request queue.
 306          *
 307          * @param pkt packet to check against
 308          *
 309          * @return true if we find a match
 310          */
 311         bool checkFunctional(PacketPtr pkt);
 312
 313       protected:
 314
 315         /** When receiving a timing request from the peer port,
 316             pass it to the bridge. */
 317         bool recvTimingResp(PacketPtr pkt);
 318
 319         /** When receiving a retry request from the peer port,
 320             pass it to the bridge. */
 321         void recvRetry();
 322     };
 323
 324     /** Slave port of the bridge. */
 325     BridgeSlavePort slavePort;
 326
 327     /** Master port of the bridge. */
 328     BridgeMasterPort masterPort;
 329
 330   public:
 331
 332     virtual BaseMasterPort& getMasterPort(const std::string& if_name,
 333                                           PortID idx = InvalidPortID);
 334     virtual BaseSlavePort& getSlavePort(const std::string& if_name,
 335                                         PortID idx = InvalidPortID);
 336
 337     virtual void init();
 338
 339     typedef BridgeParams Params;
 340
 341     Bridge(Params *p);
 342 };
 343
 344 #endif //__MEM_BRIDGE_HH__