src/mem/bridge.hh

   1 /*
   2  * Copyright (c) 2011-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  *          Steve Reinhardt
  42  *          Andreas Hansson
  43  */
  44
  45 /**
  46  * @file
  47  * Declaration of a memory-mapped bridge that connects a master
  48  * and a slave through a request and response queue.
  49  */
  50
  51 #ifndef __MEM_BRIDGE_HH__
  52 #define __MEM_BRIDGE_HH__
  53
  54 #include <deque>
  55
  56 #include "base/types.hh"
  57 #include "mem/mem_object.hh"
  58 #include "params/Bridge.hh"
  59
  60 /**
  61  * A bridge is used to interface two different crossbars (or in general a
  62  * memory-mapped master and slave), with buffering for requests and
  63  * responses. The bridge has a fixed delay for packets passing through
  64  * it and responds to a fixed set of address ranges.
  65  *
  66  * The bridge comprises a slave port and a master port, that buffer
  67  * outgoing responses and requests respectively. Buffer space is
  68  * reserved when a request arrives, also reserving response space
  69  * before forwarding the request. If there is no space present, then
  70  * the bridge will delay accepting the packet until space becomes
  71  * available.
  72  */
  73 class Bridge : public MemObject
  74 {
  75   protected:
  76
  77     /**
  78      * A deferred packet stores a packet along with its scheduled
  79      * transmission time
  80      */
  81     class DeferredPacket
  82     {
  83
  84       public:
  85
  86         const Tick tick;
  87         const PacketPtr pkt;
  88
  89         DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
  90         { }
  91     };
  92
  93     // Forward declaration to allow the slave port to have a pointer
  94     class BridgeMasterPort;
  95
  96     /**
  97      * The port on the side that receives requests and sends
  98      * responses. The slave port has a set of address ranges that it
  99      * is responsible for. The slave port also has a buffer for the
 100      * responses not yet sent.
 101      */
 102     class BridgeSlavePort : public SlavePort
 103     {
 104
 105       private:
 106
 107         /** The bridge to which this port belongs. */
 108         Bridge& bridge;
 109
 110         /**
 111          * Master port on the other side of the bridge.
 112          */
 113         BridgeMasterPort& masterPort;
 114
 115         /** Minimum request delay though this bridge. */
 116         const Cycles delay;
 117
 118         /** Address ranges to pass through the bridge */
 119         const AddrRangeList ranges;
 120
 121         /**
 122          * Response packet queue. Response packets are held in this
 123          * queue for a specified delay to model the processing delay
 124          * of the bridge. We use a deque as we need to iterate over
 125          * the items for functional accesses.
 126          */
 127         std::deque<DeferredPacket> transmitList;
 128
 129         /** Counter to track the outstanding responses. */
 130         unsigned int outstandingResponses;
 131
 132         /** If we should send a retry when space becomes available. */
 133         bool retryReq;
 134
 135         /** Max queue size for reserved responses. */
 136         unsigned int respQueueLimit;
 137
 138         /**
 139          * Upstream caches need this packet until true is returned, so
 140          * hold it for deletion until a subsequent call
 141          */
 142         std::unique_ptr<Packet> pendingDelete;
 143
 144         /**
 145          * Is this side blocked from accepting new response packets.
 146          *
 147          * @return true if the reserved space has reached the set limit
 148          */
 149         bool respQueueFull() const;
 150
 151         /**
 152          * Handle send event, scheduled when the packet at the head of
 153          * the response queue is ready to transmit (for timing
 154          * accesses only).
 155          */
 156         void trySendTiming();
 157
 158         /** Send event for the response queue. */
 159         EventWrapper<BridgeSlavePort,
 160                      &BridgeSlavePort::trySendTiming> sendEvent;
 161
 162       public:
 163
 164         /**
 165          * Constructor for the BridgeSlavePort.
 166          *
 167          * @param _name the port name including the owner
 168          * @param _bridge the structural owner
 169          * @param _masterPort the master port on the other side of the bridge
 170          * @param _delay the delay in cycles from receiving to sending
 171          * @param _resp_limit the size of the response queue
 172          * @param _ranges a number of address ranges to forward
 173          */
 174         BridgeSlavePort(const std::string& _name, Bridge& _bridge,
 175                         BridgeMasterPort& _masterPort, Cycles _delay,
 176                         int _resp_limit, std::vector<AddrRange> _ranges);
 177
 178         /**
 179          * Queue a response packet to be sent out later and also schedule
 180          * a send if necessary.
 181          *
 182          * @param pkt a response to send out after a delay
 183          * @param when tick when response packet should be sent
 184          */
 185         void schedTimingResp(PacketPtr pkt, Tick when);
 186
 187         /**
 188          * Retry any stalled request that we have failed to accept at
 189          * an earlier point in time. This call will do nothing if no
 190          * request is waiting.
 191          */
 192         void retryStalledReq();
 193
 194       protected:
 195
 196         /** When receiving a timing request from the peer port,
 197             pass it to the bridge. */
 198         bool recvTimingReq(PacketPtr pkt);
 199
 200         /** When receiving a retry request from the peer port,
 201             pass it to the bridge. */
 202         void recvRespRetry();
 203
 204         /** When receiving a Atomic requestfrom the peer port,
 205             pass it to the bridge. */
 206         Tick recvAtomic(PacketPtr pkt);
 207
 208         /** When receiving a Functional request from the peer port,
 209             pass it to the bridge. */
 210         void recvFunctional(PacketPtr pkt);
 211
 212         /** When receiving a address range request the peer port,
 213             pass it to the bridge. */
 214         AddrRangeList getAddrRanges() const;
 215     };
 216
 217
 218     /**
 219      * Port on the side that forwards requests and receives
 220      * responses. The master port has a buffer for the requests not
 221      * yet sent.
 222      */
 223     class BridgeMasterPort : public MasterPort
 224     {
 225
 226       private:
 227
 228         /** The bridge to which this port belongs. */
 229         Bridge& bridge;
 230
 231         /**
 232          * The slave port on the other side of the bridge.
 233          */
 234         BridgeSlavePort& slavePort;
 235
 236         /** Minimum delay though this bridge. */
 237         const Cycles delay;
 238
 239         /**
 240          * Request packet queue. Request packets are held in this
 241          * queue for a specified delay to model the processing delay
 242          * of the bridge.  We use a deque as we need to iterate over
 243          * the items for functional accesses.
 244          */
 245         std::deque<DeferredPacket> transmitList;
 246
 247         /** Max queue size for request packets */
 248         const unsigned int reqQueueLimit;
 249
 250         /**
 251          * Handle send event, scheduled when the packet at the head of
 252          * the outbound queue is ready to transmit (for timing
 253          * accesses only).
 254          */
 255         void trySendTiming();
 256
 257         /** Send event for the request queue. */
 258         EventWrapper<BridgeMasterPort,
 259                      &BridgeMasterPort::trySendTiming> sendEvent;
 260
 261       public:
 262
 263         /**
 264          * Constructor for the BridgeMasterPort.
 265          *
 266          * @param _name the port name including the owner
 267          * @param _bridge the structural owner
 268          * @param _slavePort the slave port on the other side of the bridge
 269          * @param _delay the delay in cycles from receiving to sending
 270          * @param _req_limit the size of the request queue
 271          */
 272         BridgeMasterPort(const std::string& _name, Bridge& _bridge,
 273                          BridgeSlavePort& _slavePort, Cycles _delay,
 274                          int _req_limit);
 275
 276         /**
 277          * Is this side blocked from accepting new request packets.
 278          *
 279          * @return true if the occupied space has reached the set limit
 280          */
 281         bool reqQueueFull() const;
 282
 283         /**
 284          * Queue a request packet to be sent out later and also schedule
 285          * a send if necessary.
 286          *
 287          * @param pkt a request to send out after a delay
 288          * @param when tick when response packet should be sent
 289          */
 290         void schedTimingReq(PacketPtr pkt, Tick when);
 291
 292         /**
 293          * Check a functional request against the packets in our
 294          * request queue.
 295          *
 296          * @param pkt packet to check against
 297          *
 298          * @return true if we find a match
 299          */
 300         bool checkFunctional(PacketPtr pkt);
 301
 302       protected:
 303
 304         /** When receiving a timing request from the peer port,
 305             pass it to the bridge. */
 306         bool recvTimingResp(PacketPtr pkt);
 307
 308         /** When receiving a retry request from the peer port,
 309             pass it to the bridge. */
 310         void recvReqRetry();
 311     };
 312
 313     /** Slave port of the bridge. */
 314     BridgeSlavePort slavePort;
 315
 316     /** Master port of the bridge. */
 317     BridgeMasterPort masterPort;
 318
 319   public:
 320
 321     virtual BaseMasterPort& getMasterPort(const std::string& if_name,
 322                                           PortID idx = InvalidPortID);
 323     virtual BaseSlavePort& getSlavePort(const std::string& if_name,
 324                                         PortID idx = InvalidPortID);
 325
 326     virtual void init();
 327
 328     typedef BridgeParams Params;
 329
 330     Bridge(Params *p);
 331 };
 332
 333 #endif //__MEM_BRIDGE_HH__