src/mem/bridge.hh

   1 /*
   2  * Copyright (c) 2011-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /**
  42  * @file
  43  * Declaration of a memory-mapped bridge that connects a master
  44  * and a slave through a request and response queue.
  45  */
  46
  47 #ifndef __MEM_BRIDGE_HH__
  48 #define __MEM_BRIDGE_HH__
  49
  50 #include <deque>
  51
  52 #include "base/types.hh"
  53 #include "mem/port.hh"
  54 #include "params/Bridge.hh"
  55 #include "sim/clocked_object.hh"
  56
  57 /**
  58  * A bridge is used to interface two different crossbars (or in general a
  59  * memory-mapped master and slave), with buffering for requests and
  60  * responses. The bridge has a fixed delay for packets passing through
  61  * it and responds to a fixed set of address ranges.
  62  *
  63  * The bridge comprises a slave port and a master port, that buffer
  64  * outgoing responses and requests respectively. Buffer space is
  65  * reserved when a request arrives, also reserving response space
  66  * before forwarding the request. If there is no space present, then
  67  * the bridge will delay accepting the packet until space becomes
  68  * available.
  69  */
  70 class Bridge : public ClockedObject
  71 {
  72   protected:
  73
  74     /**
  75      * A deferred packet stores a packet along with its scheduled
  76      * transmission time
  77      */
  78     class DeferredPacket
  79     {
  80
  81       public:
  82
  83         const Tick tick;
  84         const PacketPtr pkt;
  85
  86         DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
  87         { }
  88     };
  89
  90     // Forward declaration to allow the slave port to have a pointer
  91     class BridgeMasterPort;
  92
  93     /**
  94      * The port on the side that receives requests and sends
  95      * responses. The slave port has a set of address ranges that it
  96      * is responsible for. The slave port also has a buffer for the
  97      * responses not yet sent.
  98      */
  99     class BridgeSlavePort : public ResponsePort
 100     {
 101
 102       private:
 103
 104         /** The bridge to which this port belongs. */
 105         Bridge& bridge;
 106
 107         /**
 108          * Master port on the other side of the bridge.
 109          */
 110         BridgeMasterPort& masterPort;
 111
 112         /** Minimum request delay though this bridge. */
 113         const Cycles delay;
 114
 115         /** Address ranges to pass through the bridge */
 116         const AddrRangeList ranges;
 117
 118         /**
 119          * Response packet queue. Response packets are held in this
 120          * queue for a specified delay to model the processing delay
 121          * of the bridge. We use a deque as we need to iterate over
 122          * the items for functional accesses.
 123          */
 124         std::deque<DeferredPacket> transmitList;
 125
 126         /** Counter to track the outstanding responses. */
 127         unsigned int outstandingResponses;
 128
 129         /** If we should send a retry when space becomes available. */
 130         bool retryReq;
 131
 132         /** Max queue size for reserved responses. */
 133         unsigned int respQueueLimit;
 134
 135         /**
 136          * Upstream caches need this packet until true is returned, so
 137          * hold it for deletion until a subsequent call
 138          */
 139         std::unique_ptr<Packet> pendingDelete;
 140
 141         /**
 142          * Is this side blocked from accepting new response packets.
 143          *
 144          * @return true if the reserved space has reached the set limit
 145          */
 146         bool respQueueFull() const;
 147
 148         /**
 149          * Handle send event, scheduled when the packet at the head of
 150          * the response queue is ready to transmit (for timing
 151          * accesses only).
 152          */
 153         void trySendTiming();
 154
 155         /** Send event for the response queue. */
 156         EventFunctionWrapper sendEvent;
 157
 158       public:
 159
 160         /**
 161          * Constructor for the BridgeSlavePort.
 162          *
 163          * @param _name the port name including the owner
 164          * @param _bridge the structural owner
 165          * @param _masterPort the master port on the other side of the bridge
 166          * @param _delay the delay in cycles from receiving to sending
 167          * @param _resp_limit the size of the response queue
 168          * @param _ranges a number of address ranges to forward
 169          */
 170         BridgeSlavePort(const std::string& _name, Bridge& _bridge,
 171                         BridgeMasterPort& _masterPort, Cycles _delay,
 172                         int _resp_limit, std::vector<AddrRange> _ranges);
 173
 174         /**
 175          * Queue a response packet to be sent out later and also schedule
 176          * a send if necessary.
 177          *
 178          * @param pkt a response to send out after a delay
 179          * @param when tick when response packet should be sent
 180          */
 181         void schedTimingResp(PacketPtr pkt, Tick when);
 182
 183         /**
 184          * Retry any stalled request that we have failed to accept at
 185          * an earlier point in time. This call will do nothing if no
 186          * request is waiting.
 187          */
 188         void retryStalledReq();
 189
 190       protected:
 191
 192         /** When receiving a timing request from the peer port,
 193             pass it to the bridge. */
 194         bool recvTimingReq(PacketPtr pkt);
 195
 196         /** When receiving a retry request from the peer port,
 197             pass it to the bridge. */
 198         void recvRespRetry();
 199
 200         /** When receiving a Atomic requestfrom the peer port,
 201             pass it to the bridge. */
 202         Tick recvAtomic(PacketPtr pkt);
 203
 204         /** When receiving a Functional request from the peer port,
 205             pass it to the bridge. */
 206         void recvFunctional(PacketPtr pkt);
 207
 208         /** When receiving a address range request the peer port,
 209             pass it to the bridge. */
 210         AddrRangeList getAddrRanges() const;
 211     };
 212
 213
 214     /**
 215      * Port on the side that forwards requests and receives
 216      * responses. The master port has a buffer for the requests not
 217      * yet sent.
 218      */
 219     class BridgeMasterPort : public RequestPort
 220     {
 221
 222       private:
 223
 224         /** The bridge to which this port belongs. */
 225         Bridge& bridge;
 226
 227         /**
 228          * The slave port on the other side of the bridge.
 229          */
 230         BridgeSlavePort& slavePort;
 231
 232         /** Minimum delay though this bridge. */
 233         const Cycles delay;
 234
 235         /**
 236          * Request packet queue. Request packets are held in this
 237          * queue for a specified delay to model the processing delay
 238          * of the bridge.  We use a deque as we need to iterate over
 239          * the items for functional accesses.
 240          */
 241         std::deque<DeferredPacket> transmitList;
 242
 243         /** Max queue size for request packets */
 244         const unsigned int reqQueueLimit;
 245
 246         /**
 247          * Handle send event, scheduled when the packet at the head of
 248          * the outbound queue is ready to transmit (for timing
 249          * accesses only).
 250          */
 251         void trySendTiming();
 252
 253         /** Send event for the request queue. */
 254         EventFunctionWrapper sendEvent;
 255
 256       public:
 257
 258         /**
 259          * Constructor for the BridgeMasterPort.
 260          *
 261          * @param _name the port name including the owner
 262          * @param _bridge the structural owner
 263          * @param _slavePort the slave port on the other side of the bridge
 264          * @param _delay the delay in cycles from receiving to sending
 265          * @param _req_limit the size of the request queue
 266          */
 267         BridgeMasterPort(const std::string& _name, Bridge& _bridge,
 268                          BridgeSlavePort& _slavePort, Cycles _delay,
 269                          int _req_limit);
 270
 271         /**
 272          * Is this side blocked from accepting new request packets.
 273          *
 274          * @return true if the occupied space has reached the set limit
 275          */
 276         bool reqQueueFull() const;
 277
 278         /**
 279          * Queue a request packet to be sent out later and also schedule
 280          * a send if necessary.
 281          *
 282          * @param pkt a request to send out after a delay
 283          * @param when tick when response packet should be sent
 284          */
 285         void schedTimingReq(PacketPtr pkt, Tick when);
 286
 287         /**
 288          * Check a functional request against the packets in our
 289          * request queue.
 290          *
 291          * @param pkt packet to check against
 292          *
 293          * @return true if we find a match
 294          */
 295         bool trySatisfyFunctional(PacketPtr pkt);
 296
 297       protected:
 298
 299         /** When receiving a timing request from the peer port,
 300             pass it to the bridge. */
 301         bool recvTimingResp(PacketPtr pkt);
 302
 303         /** When receiving a retry request from the peer port,
 304             pass it to the bridge. */
 305         void recvReqRetry();
 306     };
 307
 308     /** Slave port of the bridge. */
 309     BridgeSlavePort slavePort;
 310
 311     /** Master port of the bridge. */
 312     BridgeMasterPort masterPort;
 313
 314   public:
 315
 316     Port &getPort(const std::string &if_name,
 317                   PortID idx=InvalidPortID) override;
 318
 319     void init() override;
 320
 321     typedef BridgeParams Params;
 322
 323     Bridge(Params *p);
 324 };
 325
 326 #endif //__MEM_BRIDGE_HH__