4f330230f5a995678ebca30fe30054c8d96883a5
[gem5.git] / src / mem / bus.hh
1 /*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ron Dreslinski
29 * Ali Saidi
30 */
31
32 /**
33 * @file
34 * Declaration of a bus object.
35 */
36
37 #ifndef __MEM_BUS_HH__
38 #define __MEM_BUS_HH__
39
40 #include <string>
41 #include <list>
42 #include <inttypes.h>
43
44 #include "base/range.hh"
45 #include "mem/mem_object.hh"
46 #include "mem/packet.hh"
47 #include "mem/port.hh"
48 #include "mem/request.hh"
49 #include "sim/eventq.hh"
50
51 class Bus : public MemObject
52 {
53 /** a globally unique id for this bus. */
54 int busId;
55 /** the clock speed for the bus */
56 int clock;
57 /** the width of the bus in bytes */
58 int width;
59 /** the next tick at which the bus will be idle */
60 Tick tickNextIdle;
61
62 static const int defaultId = -1;
63
64 struct DevMap {
65 int portId;
66 Range<Addr> range;
67 };
68 std::vector<DevMap> portList;
69 AddrRangeList defaultRange;
70 std::vector<DevMap> portSnoopList;
71
72 /** Function called by the port when the bus is recieving a Timing
73 transaction.*/
74 bool recvTiming(Packet *pkt);
75
76 /** Function called by the port when the bus is recieving a Atomic
77 transaction.*/
78 Tick recvAtomic(Packet *pkt);
79
80 /** Function called by the port when the bus is recieving a Functional
81 transaction.*/
82 void recvFunctional(Packet *pkt);
83
84 /** Timing function called by port when it is once again able to process
85 * requests. */
86 void recvRetry(int id);
87
88 /** Function called by the port when the bus is recieving a status change.*/
89 void recvStatusChange(Port::Status status, int id);
90
91 /** Find which port connected to this bus (if any) should be given a packet
92 * with this address.
93 * @param addr Address to find port for.
94 * @param id Id of the port this packet was received from (to prevent
95 * loops)
96 * @return pointer to port that the packet should be sent out of.
97 */
98 Port *findPort(Addr addr, int id);
99
100 /** Find all ports with a matching snoop range, except src port. Keep in mind
101 * that the ranges shouldn't overlap or you will get a double snoop to the same
102 * interface.and the cache will assert out.
103 * @param addr Address to find snoop prts for.
104 * @param id Id of the src port of the request to avoid calling snoop on src
105 * @return vector of IDs to snoop on
106 */
107 std::vector<int> findSnoopPorts(Addr addr, int id);
108
109 /** Snoop all relevant ports atomicly. */
110 void atomicSnoop(Packet *pkt);
111
112 /** Snoop all relevant ports functionally. */
113 void functionalSnoop(Packet *pkt);
114
115 /** Call snoop on caches, be sure to set SNOOP_COMMIT bit if you want
116 * the snoop to happen
117 * @return True if succeds.
118 */
119 bool timingSnoop(Packet *pkt);
120
121 /** Process address range request.
122 * @param resp addresses that we can respond to
123 * @param snoop addresses that we would like to snoop
124 * @param id ide of the busport that made the request.
125 */
126 void addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id);
127
128
129 /** Declaration of the buses port type, one will be instantiated for each
130 of the interfaces connecting to the bus. */
131 class BusPort : public Port
132 {
133 bool _onRetryList;
134
135 /** A pointer to the bus to which this port belongs. */
136 Bus *bus;
137
138 /** A id to keep track of the intercafe ID this port is connected to. */
139 int id;
140
141 public:
142
143 /** Constructor for the BusPort.*/
144 BusPort(const std::string &_name, Bus *_bus, int _id)
145 : Port(_name), _onRetryList(false), bus(_bus), id(_id)
146 { }
147
148 bool onRetryList()
149 { return _onRetryList; }
150
151 void onRetryList(bool newVal)
152 { _onRetryList = newVal; }
153
154 protected:
155
156 /** When reciving a timing request from the peer port (at id),
157 pass it to the bus. */
158 virtual bool recvTiming(Packet *pkt)
159 { pkt->setSrc(id); return bus->recvTiming(pkt); }
160
161 /** When reciving a Atomic requestfrom the peer port (at id),
162 pass it to the bus. */
163 virtual Tick recvAtomic(Packet *pkt)
164 { pkt->setSrc(id); return bus->recvAtomic(pkt); }
165
166 /** When reciving a Functional requestfrom the peer port (at id),
167 pass it to the bus. */
168 virtual void recvFunctional(Packet *pkt)
169 { pkt->setSrc(id); bus->recvFunctional(pkt); }
170
171 /** When reciving a status changefrom the peer port (at id),
172 pass it to the bus. */
173 virtual void recvStatusChange(Status status)
174 { bus->recvStatusChange(status, id); }
175
176 /** When reciving a retry from the peer port (at id),
177 pass it to the bus. */
178 virtual void recvRetry()
179 { bus->recvRetry(id); }
180
181 // This should return all the 'owned' addresses that are
182 // downstream from this bus, yes? That is, the union of all
183 // the 'owned' address ranges of all the other interfaces on
184 // this bus...
185 virtual void getDeviceAddressRanges(AddrRangeList &resp,
186 AddrRangeList &snoop)
187 { bus->addressRanges(resp, snoop, id); }
188
189 // Hack to make translating port work without changes
190 virtual int deviceBlockSize() { return 32; }
191
192 };
193
194 class BusFreeEvent : public Event
195 {
196 Bus * bus;
197
198 public:
199 BusFreeEvent(Bus * _bus);
200 void process();
201 const char *description();
202 };
203
204 BusFreeEvent busIdle;
205
206 bool inRetry;
207
208 /** An array of pointers to the peer port interfaces
209 connected to this bus.*/
210 std::vector<BusPort*> interfaces;
211
212 /** An array of pointers to ports that retry should be called on because the
213 * original send failed for whatever reason.*/
214 std::list<BusPort*> retryList;
215
216 void addToRetryList(BusPort * port)
217 {
218 if (!inRetry) {
219 // The device wasn't retrying a packet, or wasn't at an appropriate
220 // time.
221 assert(!port->onRetryList());
222 port->onRetryList(true);
223 retryList.push_back(port);
224 } else {
225 // The device was retrying a packet. It didn't work, so we'll leave
226 // it at the head of the retry list.
227 inRetry = false;
228
229 /* // We shouldn't be receiving a packet from one port when a different
230 // one is retrying.
231 assert(port == retryingPort);*/
232 }
233 }
234
235 /** Port that handles requests that don't match any of the interfaces.*/
236 Port *defaultPort;
237
238 public:
239
240 /** A function used to return the port associated with this bus object. */
241 virtual Port *getPort(const std::string &if_name, int idx = -1);
242
243 virtual void init();
244
245 Bus(const std::string &n, int bus_id, int _clock, int _width)
246 : MemObject(n), busId(bus_id), clock(_clock), width(_width),
247 tickNextIdle(0), busIdle(this), inRetry(false), defaultPort(NULL)
248 {
249 //Both the width and clock period must be positive
250 if (width <= 0)
251 fatal("Bus width must be positive\n");
252 if (clock <= 0)
253 fatal("Bus clock period must be positive\n");
254 }
255
256 };
257
258 #endif //__MEM_BUS_HH__