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40 * Authors: Ron Dreslinski
48 * Declaration of an abstract bus base class.
51 #ifndef __MEM_BUS_HH__
52 #define __MEM_BUS_HH__
57 #include "base/addr_range_map.hh"
58 #include "base/types.hh"
59 #include "mem/mem_object.hh"
60 #include "params/BaseBus.hh"
63 * The base bus contains the common elements of the non-coherent and
64 * coherent bus. It is an abstract class that does not have any of the
65 * functionality relating to the actual reception and transmission of
66 * packets, as this is left for the subclasses.
68 * The BaseBus is responsible for the basic flow control (busy or
69 * not), the administration of retries, and the address decoding.
71 class BaseBus : public MemObject
77 * A bus layer is an internal bus structure with its own flow
78 * control and arbitration. Hence, a single-layer bus mimics a
79 * traditional off-chip tri-state bus (like PCI), where only one
80 * set of wires are shared. For on-chip buses, a good starting
81 * point is to have three layers, for requests, responses, and
82 * snoop responses respectively (snoop requests are instantaneous
83 * and do not need any flow control or arbitration). This case is
84 * similar to AHB and some OCP configurations.
86 * As a further extensions beyond the three-layer bus, a future
87 * multi-layer bus has with one layer per connected slave port
88 * provides a full or partial crossbar, like AXI, OCP, PCIe etc.
90 * The template parameter, PortClass, indicates the destination
91 * port type for the bus. The retry list holds either master ports
92 * or slave ports, depending on the direction of the layer. Thus,
93 * a request layer has a retry list containing slave ports,
94 * whereas a response layer holds master ports.
96 template <typename PortClass>
103 * Create a bus layer and give it a name. The bus layer uses
104 * the bus an event manager.
106 * @param _bus the bus this layer belongs to
107 * @param _name the layer's name
108 * @param _clock clock period in ticks
110 Layer(BaseBus& _bus, const std::string& _name, Tick _clock);
113 * Drain according to the normal semantics, so that the bus
114 * can tell the layer to drain, and pass an event to signal
117 * @param de drain event to call once drained
119 * @return 1 if busy or waiting to retry, or 0 if idle
121 unsigned int drain(Event *de);
124 * Get the bus layer's name
126 const std::string name() const { return bus.name() + _name; }
130 * Determine if the bus layer accepts a packet from a specific
131 * port. If not, the port in question is also added to the
132 * retry list. In either case the state of the layer is updated
135 * @param port Source port resenting the packet
137 * @return True if the bus layer accepts the packet
139 bool tryTiming(PortClass* port);
142 * Deal with a destination port accepting a packet by potentially
143 * removing the source port from the retry list (if retrying) and
144 * occupying the bus layer accordingly.
146 * @param busy_time Time to spend as a result of a successful send
148 void succeededTiming(Tick busy_time);
151 * Deal with a destination port not accepting a packet by
152 * potentially adding the source port to the retry list (if
153 * not already at the front) and occupying the bus layer
156 * @param busy_time Time to spend as a result of a failed send
158 void failedTiming(PortClass* port, Tick busy_time);
160 /** Occupy the bus layer until until */
161 void occupyLayer(Tick until);
164 * Send a retry to the port at the head of the retryList. The
165 * caller must ensure that the list is not empty.
170 * Handler a retry from a neighbouring module. Eventually this
171 * should be all encapsulated in the bus. This wraps
172 * retryWaiting by verifying that there are ports waiting
173 * before calling retryWaiting.
179 /** The bus this layer is a part of. */
182 /** A name for this layer. */
186 * We declare an enum to track the state of the bus layer. The
187 * starting point is an idle state where the bus layer is
188 * waiting for a packet to arrive. Upon arrival, the bus layer
189 * transitions to the busy state, where it remains either
190 * until the packet transfer is done, or the header time is
191 * spent. Once the bus layer leaves the busy state, it can
192 * either go back to idle, if no packets have arrived while it
193 * was busy, or the bus layer goes on to retry the first port
194 * on the retryList. A similar transition takes place from
195 * idle to retry if the bus layer receives a retry from one of
196 * its connected ports. The retry state lasts until the port
197 * in questions calls sendTiming and returns control to the
198 * bus layer, or goes to a busy state if the port does not
199 * immediately react to the retry by calling sendTiming.
201 enum State { IDLE, BUSY, RETRY };
203 /** track the state of the bus layer */
206 /** the clock speed for the bus layer */
209 /** event for signalling when drained */
213 * An array of ports that retry should be called
214 * on because the original send failed for whatever reason.
216 std::list<PortClass*> retryList;
219 * Release the bus layer after being occupied and return to an
220 * idle state where we proceed to send a retry to any
221 * potential waiting port, or drain if asked to do so.
225 /** event used to schedule a release of the layer */
226 EventWrapper<Layer, &Layer::releaseLayer> releaseEvent;
230 /** cycles of overhead per transaction */
231 const Cycles headerCycles;
232 /** the width of the bus in bytes */
233 const uint32_t width;
235 typedef AddrRangeMap<PortID>::iterator PortMapIter;
236 typedef AddrRangeMap<PortID>::const_iterator PortMapConstIter;
237 AddrRangeMap<PortID> portMap;
239 AddrRangeList defaultRange;
242 * Function called by the port when the bus is recieving a range change.
244 * @param master_port_id id of the port that received the change
246 void recvRangeChange(PortID master_port_id);
248 /** Find which port connected to this bus (if any) should be given a packet
250 * @param addr Address to find port for.
251 * @return id of port that the packet should be sent out of.
253 PortID findPort(Addr addr);
255 // Cache for the findPort function storing recently used ports from portMap
263 PortCache portCache[3];
265 // Checks the cache and returns the id of the port that has the requested
266 // address within its range
267 inline PortID checkPortCache(Addr addr) {
268 if (portCache[0].valid && addr >= portCache[0].start &&
269 addr < portCache[0].end) {
270 return portCache[0].id;
272 if (portCache[1].valid && addr >= portCache[1].start &&
273 addr < portCache[1].end) {
274 return portCache[1].id;
276 if (portCache[2].valid && addr >= portCache[2].start &&
277 addr < portCache[2].end) {
278 return portCache[2].id;
281 return InvalidPortID;
284 // Clears the earliest entry of the cache and inserts a new port entry
285 inline void updatePortCache(short id, Addr start, Addr end) {
286 portCache[2].valid = portCache[1].valid;
287 portCache[2].id = portCache[1].id;
288 portCache[2].start = portCache[1].start;
289 portCache[2].end = portCache[1].end;
291 portCache[1].valid = portCache[0].valid;
292 portCache[1].id = portCache[0].id;
293 portCache[1].start = portCache[0].start;
294 portCache[1].end = portCache[0].end;
296 portCache[0].valid = true;
297 portCache[0].id = id;
298 portCache[0].start = start;
299 portCache[0].end = end;
302 // Clears the cache. Needs to be called in constructor.
303 inline void clearPortCache() {
304 portCache[2].valid = false;
305 portCache[1].valid = false;
306 portCache[0].valid = false;
310 * Return the address ranges the bus is responsible for.
312 * @return a list of non-overlapping address ranges
314 AddrRangeList getAddrRanges() const;
316 /** Calculate the timing parameters for the packet. Updates the
317 * firstWordTime and finishTime fields of the packet object.
318 * Returns the tick at which the packet header is completed (which
319 * will be all that is sent if the target rejects the packet).
321 Tick calcPacketTiming(PacketPtr pkt);
324 * Ask everyone on the bus what their size is
326 * @return the max of all the sizes
328 unsigned findBlockSize();
330 std::set<PortID> inRecvRangeChange;
332 /** The master and slave ports of the bus */
333 std::vector<SlavePort*> slavePorts;
334 std::vector<MasterPort*> masterPorts;
336 /** Convenience typedefs. */
337 typedef std::vector<SlavePort*>::iterator SlavePortIter;
338 typedef std::vector<MasterPort*>::iterator MasterPortIter;
339 typedef std::vector<SlavePort*>::const_iterator SlavePortConstIter;
340 typedef std::vector<MasterPort*>::const_iterator MasterPortConstIter;
342 /** Port that handles requests that don't match any of the interfaces.*/
343 PortID defaultPortID;
345 /** If true, use address range provided by default device. Any
346 address not handled by another port and not in default device's
347 range will cause a fatal error. If false, just send all
348 addresses not handled by another port to default device. */
349 const bool useDefaultRange;
351 const uint32_t defaultBlockSize;
352 uint32_t cachedBlockSize;
353 bool cachedBlockSizeValid;
355 BaseBus(const BaseBusParams *p);
361 /** A function used to return the port associated with this bus object. */
362 virtual MasterPort& getMasterPort(const std::string& if_name, int idx = -1);
363 virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
365 virtual unsigned int drain(Event *de) = 0;
369 #endif //__MEM_BUS_HH__