src/mem/cache/BaseCache.py

   1 # Copyright (c) 2005-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Nathan Binkert
  28
  29 from m5.params import *
  30 from m5.proxy import Self
  31 from MemObject import MemObject
  32
  33 class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
  34
  35 class BaseCache(MemObject):
  36     type = 'BaseCache'
  37     adaptive_compression = Param.Bool(False,
  38         "Use an adaptive compression scheme")
  39     assoc = Param.Int("associativity")
  40     block_size = Param.Int("block size in bytes")
  41     latency = Param.Latency("Latency")
  42     compressed_bus = Param.Bool(False,
  43         "This cache connects to a compressed memory")
  44     compression_latency = Param.Latency('0ns',
  45         "Latency in cycles of compression algorithm")
  46     hash_delay = Param.Int(1, "time in cycles of hash access")
  47     lifo = Param.Bool(False,
  48         "whether this NIC partition should use LIFO repl. policy")
  49     max_miss_count = Param.Counter(0,
  50         "number of misses to handle before calling exit")
  51     mshrs = Param.Int("number of MSHRs (max outstanding requests)")
  52     prioritizeRequests = Param.Bool(False,
  53         "always service demand misses first")
  54     protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
  55     repl = Param.Repl(NULL, "replacement policy")
  56     size = Param.MemorySize("capacity in bytes")
  57     split = Param.Bool(False, "whether or not this cache is split")
  58     split_size = Param.Int(0,
  59         "How many ways of the cache belong to CPU/LRU partition")
  60     store_compressed = Param.Bool(False,
  61         "Store compressed data in the cache")
  62     subblock_size = Param.Int(0,
  63         "Size of subblock in IIC used for compression")
  64     tgts_per_mshr = Param.Int("max number of accesses per MSHR")
  65     trace_addr = Param.Addr(0, "address to trace")
  66     two_queue = Param.Bool(False,
  67         "whether the lifo should have two queue replacement")
  68     write_buffers = Param.Int(8, "number of write buffers")
  69     prefetch_miss = Param.Bool(False,
  70          "wheter you are using the hardware prefetcher from Miss stream")
  71     prefetch_access = Param.Bool(False,
  72          "wheter you are using the hardware prefetcher from Access stream")
  73     prefetcher_size = Param.Int(100,
  74          "Number of entries in the harware prefetch queue")
  75     prefetch_past_page = Param.Bool(False,
  76          "Allow prefetches to cross virtual page boundaries")
  77     prefetch_serial_squash = Param.Bool(False,
  78          "Squash prefetches with a later time on a subsequent miss")
  79     prefetch_degree = Param.Int(1,
  80          "Degree of the prefetch depth")
  81     prefetch_latency = Param.Latency(10 * Self.latency,
  82          "Latency of the prefetcher")
  83     prefetch_policy = Param.Prefetch('none',
  84          "Type of prefetcher to use")
  85     prefetch_cache_check_push = Param.Bool(True,
  86          "Check if in cash on push or pop of prefetch queue")
  87     prefetch_use_cpu_id = Param.Bool(True,
  88          "Use the CPU ID to seperate calculations of prefetches")
  89     prefetch_data_accesses_only = Param.Bool(False,
  90          "Only prefetch on data not on instruction accesses")
  91     cpu_side = Port("Port on side closer to CPU")
  92     mem_side = Port("Port on side closer to MEM")
  93     addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes")