src/mem/cache/BaseCache.py

   1 # Copyright (c) 2012-2013 ARM Limited
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  13 # Copyright (c) 2005-2007 The Regents of The University of Michigan
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  39 # Authors: Nathan Binkert
  40
  41 from m5.params import *
  42 from m5.proxy import *
  43 from MemObject import MemObject
  44 from Prefetcher import BasePrefetcher
  45 from Tags import *
  46
  47 class BaseCache(MemObject):
  48     type = 'BaseCache'
  49     cxx_header = "mem/cache/base.hh"
  50     assoc = Param.Int("associativity")
  51     hit_latency = Param.Cycles("The hit latency for this cache")
  52     response_latency = Param.Cycles(
  53             "Additional cache latency for the return path to core on a miss");
  54     max_miss_count = Param.Counter(0,
  55         "number of misses to handle before calling exit")
  56     mshrs = Param.Int("number of MSHRs (max outstanding requests)")
  57     size = Param.MemorySize("capacity in bytes")
  58     forward_snoops = Param.Bool(True,
  59         "forward snoops from mem side to cpu side")
  60     is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)")
  61     tgts_per_mshr = Param.Int("max number of accesses per MSHR")
  62     two_queue = Param.Bool(False,
  63         "whether the lifo should have two queue replacement")
  64     write_buffers = Param.Int(8, "number of write buffers")
  65     prefetch_on_access = Param.Bool(False,
  66          "notify the hardware prefetcher on every access (not just misses)")
  67     prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
  68     cpu_side = SlavePort("Port on side closer to CPU")
  69     mem_side = MasterPort("Port on side closer to MEM")
  70     addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port")
  71     system = Param.System(Parent.any, "System we belong to")
  72     sequential_access = Param.Bool(False,
  73         "Whether to access tags and data sequentially")
  74     tags = Param.BaseTags(LRU(), "Tag Store for LRU caches")