src/mem/cache/BaseCache.py

   1 # Copyright (c) 2005-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
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   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Nathan Binkert
  28
  29 from m5.params import *
  30 from m5.proxy import Self
  31 from MemObject import MemObject
  32
  33 class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
  34
  35 class BaseCache(MemObject):
  36     type = 'BaseCache'
  37     assoc = Param.Int("associativity")
  38     block_size = Param.Int("block size in bytes")
  39     latency = Param.Latency("Latency")
  40     hash_delay = Param.Int(1, "time in cycles of hash access")
  41     max_miss_count = Param.Counter(0,
  42         "number of misses to handle before calling exit")
  43     mshrs = Param.Int("number of MSHRs (max outstanding requests)")
  44     prioritizeRequests = Param.Bool(False,
  45         "always service demand misses first")
  46     repl = Param.Repl(NULL, "replacement policy")
  47     num_cpus =  Param.Int(1, "number of cpus sharing this cache")
  48     size = Param.MemorySize("capacity in bytes")
  49     forward_snoops = Param.Bool(True,
  50         "forward snoops from mem side to cpu side")
  51     subblock_size = Param.Int(0,
  52         "Size of subblock in IIC used for compression")
  53     tgts_per_mshr = Param.Int("max number of accesses per MSHR")
  54     trace_addr = Param.Addr(0, "address to trace")
  55     two_queue = Param.Bool(False,
  56         "whether the lifo should have two queue replacement")
  57     write_buffers = Param.Int(8, "number of write buffers")
  58     prefetch_on_access = Param.Bool(False,
  59          "notify the hardware prefetcher on every access (not just misses)")
  60     prefetcher_size = Param.Int(100,
  61          "Number of entries in the hardware prefetch queue")
  62     prefetch_past_page = Param.Bool(False,
  63          "Allow prefetches to cross virtual page boundaries")
  64     prefetch_serial_squash = Param.Bool(False,
  65          "Squash prefetches with a later time on a subsequent miss")
  66     prefetch_degree = Param.Int(1,
  67          "Degree of the prefetch depth")
  68     prefetch_latency = Param.Latency(10 * Self.latency,
  69          "Latency of the prefetcher")
  70     prefetch_policy = Param.Prefetch('none',
  71          "Type of prefetcher to use")
  72     prefetch_use_cpu_id = Param.Bool(True,
  73          "Use the CPU ID to separate calculations of prefetches")
  74     prefetch_data_accesses_only = Param.Bool(False,
  75          "Only prefetch on data not on instruction accesses")
  76     cpu_side = Port("Port on side closer to CPU")
  77     mem_side = Port("Port on side closer to MEM")
  78     addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port")