1 # Copyright (c) 2005-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Nathan Binkert
29 from m5
.params
import *
30 from m5
.proxy
import Self
31 from MemObject
import MemObject
33 class Prefetch(Enum
): vals
= ['none', 'tagged', 'stride', 'ghb']
35 class BaseCache(MemObject
):
37 assoc
= Param
.Int("associativity")
38 block_size
= Param
.Int("block size in bytes")
39 latency
= Param
.Latency("Latency")
40 hash_delay
= Param
.Int(1, "time in cycles of hash access")
41 lifo
= Param
.Bool(False,
42 "whether this NIC partition should use LIFO repl. policy")
43 max_miss_count
= Param
.Counter(0,
44 "number of misses to handle before calling exit")
45 mshrs
= Param
.Int("number of MSHRs (max outstanding requests)")
46 prioritizeRequests
= Param
.Bool(False,
47 "always service demand misses first")
48 repl
= Param
.Repl(NULL
, "replacement policy")
49 size
= Param
.MemorySize("capacity in bytes")
50 split
= Param
.Bool(False, "whether or not this cache is split")
51 split_size
= Param
.Int(0,
52 "How many ways of the cache belong to CPU/LRU partition")
53 subblock_size
= Param
.Int(0,
54 "Size of subblock in IIC used for compression")
55 tgts_per_mshr
= Param
.Int("max number of accesses per MSHR")
56 trace_addr
= Param
.Addr(0, "address to trace")
57 two_queue
= Param
.Bool(False,
58 "whether the lifo should have two queue replacement")
59 write_buffers
= Param
.Int(8, "number of write buffers")
60 prefetch_miss
= Param
.Bool(False,
61 "wheter you are using the hardware prefetcher from Miss stream")
62 prefetch_access
= Param
.Bool(False,
63 "wheter you are using the hardware prefetcher from Access stream")
64 prefetcher_size
= Param
.Int(100,
65 "Number of entries in the harware prefetch queue")
66 prefetch_past_page
= Param
.Bool(False,
67 "Allow prefetches to cross virtual page boundaries")
68 prefetch_serial_squash
= Param
.Bool(False,
69 "Squash prefetches with a later time on a subsequent miss")
70 prefetch_degree
= Param
.Int(1,
71 "Degree of the prefetch depth")
72 prefetch_latency
= Param
.Latency(10 * Self
.latency
,
73 "Latency of the prefetcher")
74 prefetch_policy
= Param
.Prefetch('none',
75 "Type of prefetcher to use")
76 prefetch_cache_check_push
= Param
.Bool(True,
77 "Check if in cash on push or pop of prefetch queue")
78 prefetch_use_cpu_id
= Param
.Bool(True,
79 "Use the CPU ID to seperate calculations of prefetches")
80 prefetch_data_accesses_only
= Param
.Bool(False,
81 "Only prefetch on data not on instruction accesses")
82 cpu_side
= Port("Port on side closer to CPU")
83 mem_side
= Port("Port on side closer to MEM")
84 cpu_side_filter_ranges
= VectorParam
.AddrRange([],
85 "What addresses shouldn't be passed through the side of the bridge")
86 mem_side_filter_ranges
= VectorParam
.AddrRange([],
87 "What addresses shouldn't be passed through the side of the bridge")
88 addr_range
= VectorParam
.AddrRange(AllMemory
, "The address range in bytes")