1 # Copyright (c) 2005-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Nathan Binkert
29 from m5
.params
import *
30 from m5
.proxy
import Self
31 from MemObject
import MemObject
33 class Prefetch(Enum
): vals
= ['none', 'tagged', 'stride', 'ghb']
35 class BaseCache(MemObject
):
37 assoc
= Param
.Int("associativity")
38 block_size
= Param
.Int("block size in bytes")
39 latency
= Param
.Latency("Latency")
40 hash_delay
= Param
.Int(1, "time in cycles of hash access")
41 max_miss_count
= Param
.Counter(0,
42 "number of misses to handle before calling exit")
43 mshrs
= Param
.Int("number of MSHRs (max outstanding requests)")
44 prioritizeRequests
= Param
.Bool(False,
45 "always service demand misses first")
46 repl
= Param
.Repl(NULL
, "replacement policy")
47 num_cpus
= Param
.Int(1, "number of cpus sharing this cache")
48 size
= Param
.MemorySize("capacity in bytes")
49 forward_snoops
= Param
.Bool(True,
50 "forward snoops from mem side to cpu side")
51 is_top_level
= Param
.Bool(False, "Is this cache at the top level (e.g. L1)")
52 subblock_size
= Param
.Int(0,
53 "Size of subblock in IIC used for compression")
54 tgts_per_mshr
= Param
.Int("max number of accesses per MSHR")
55 trace_addr
= Param
.Addr(0, "address to trace")
56 two_queue
= Param
.Bool(False,
57 "whether the lifo should have two queue replacement")
58 write_buffers
= Param
.Int(8, "number of write buffers")
59 prefetch_on_access
= Param
.Bool(False,
60 "notify the hardware prefetcher on every access (not just misses)")
61 prefetcher_size
= Param
.Int(100,
62 "Number of entries in the hardware prefetch queue")
63 prefetch_past_page
= Param
.Bool(False,
64 "Allow prefetches to cross virtual page boundaries")
65 prefetch_serial_squash
= Param
.Bool(False,
66 "Squash prefetches with a later time on a subsequent miss")
67 prefetch_degree
= Param
.Int(1,
68 "Degree of the prefetch depth")
69 prefetch_latency
= Param
.Latency(10 * Self
.latency
,
70 "Latency of the prefetcher")
71 prefetch_policy
= Param
.Prefetch('none',
72 "Type of prefetcher to use")
73 prefetch_use_cpu_id
= Param
.Bool(True,
74 "Use the CPU ID to separate calculations of prefetches")
75 prefetch_data_accesses_only
= Param
.Bool(False,
76 "Only prefetch on data not on instruction accesses")
77 cpu_side
= Port("Port on side closer to CPU")
78 mem_side
= Port("Port on side closer to MEM")
79 addr_range
= Param
.AddrRange(AllMemory
, "The address range for the CPU-side port")